P3041 Features

P3041 QorIQ Communications Processor Product Brief, Rev. 0

Freescale Semiconductor

13

3.9

Universal Serial Bus (USB) 2.0

The two USB 2.0 controllers with integrated PHY provide point-to-point connectivity complying with the

USB specification, Rev. 2.0. Each USB controller can be configured to operate as a stand-alone host, and

USB #2 can be configured as a stand-alone device, or with both host and device functions operating

simultaneously.

Key features of the USB 2.0 controller include the following:

•

Complies with USB specification, Rev. 2.0

•

Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations

•

Supports the required signaling for the USB transceiver macrocell interface (UTMI).The PHY

interfacing to the UTMI is an internal PHY.

•

Both controllers support operation as a stand-alone USB host controller

— Support USB root hub with one downstream-facing port

— Enhanced host controller interface (EHCI)-compatible

•

One controller supports operation as a stand-alone USB device

— Supports one upstream-facing port

— Supports six programmable USB endpoints

The host and device functions are both configured to support all four USB transfer types:

•

Bulk

•

Control

•

Interrupt

•

Isochronous

3.10

High-Speed Peripheral Interface Complex

All high-speed peripheral interfaces connect via 18 lanes of 5-GHz SerDes to a common crossbar switch

referred to as OCeaN. Two high-speed I/O interface standards are supported: PCI Express (PCIe), and

Serial RapidIO (sRIO). The P3041 integrates the following:

•

Four PCIe controllers

•

Two Serial RapidIO controllers

•

RapidIO message manager (RMan).

3.10.1

PCI Express Controllers

Each of the four PCIe interfaces is compliant with the PCI Express Base Specification Revision 2.0. Key

features of the PCIe interface include the following:

•

Power-on reset configuration options allow root complex or endpoint functionality.

•

The physical layer operates at 2.5 or 5 Gbaud data rate per lane.

•

Receive and transmit ports operate independently, with an aggregate theoretical bandwidth of 32

Gbps.