P3041 QorIQ Communications Processor Product Brief, Rev. 0

P3041 Features

Freescale Semiconductor

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Releases CPU 0 from reset, allowing the boot processes to begin from fast system memory.

The nonvolatile memory interfaces accessible by the PBL are as follows:

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The eLBC may be accessed by software running on the CPUs following boot; it is not dedicated to

the PBL. It also can be used for both volatile (SRAM) and nonvolatile memory as well as a control

and low-performance data port for external memory-mapped devices. See Section 3.8.2.1,

“Enhanced Local Bus Controllers (eLBC).”

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The serial memory controllers may be accessed by software running on the CPUs following boot;

they are not dedicated to the PBL. See Section 3.8.2.2, “Serial Memory Controllers.”

3.8.2.1

Enhanced Local Bus Controllers (eLBC)

The enhanced local bus controller (eLBC) port connects to a variety of external memories, DSPs, and

ASICs.

Key features of the eLBC include the following:

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Multiplexed 32-bit address and 32-bit data bus operating at up to 93 MHz

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Eight chip selects for eight external slaves

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Up to eight-beat burst transfers

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8-, 16-, or 32-bit port sizes controlled by an internal memory controller

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Three protocol engines on a per-chip-select basis

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Parity support

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Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)

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Support for parallel NAND and NOR flash

Three separate state machines share the same external pins and can be programmed separately to access

different types of devices. Some examples are as follows:

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The general-purpose chip-select machine (GPCM) controls accesses to asynchronous devices

using a simple handshake protocol.

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The user-programmable machine (UPM) can be programmed to interface to synchronous devices

or custom ASIC interfaces.

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The NAND flash control machine (FCM) further extends interface options.

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Each chip select can be configured so that the associated chip interface is controlled by the GPCM,

UPM, or FCM controller.

All controllers can be enabled simultaneously. The eLBC internally arbitrates among the controllers,

allowing each to read or write a limited amount of data before allowing another controller to use the bus.

3.8.2.2

Serial Memory Controllers

In addition to the parallel NAND and NOR flash supported by means of the eLBC, the P3041 supports

serial flash using SPI and SD/MMC card interfaces. The SD/MMC controller includes a DMA engine,

allowing it to move data from serial flash to external or internal memory following straightforward

initiation by software.