WM8776 datasheet(17/57 Pages) WOLFSON

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Production Data

WM8776

PD Rev 4.0 April 2005

AUDIO DATA SAMPLING RATES

In a typical digital audio system there is only one central clock source producing a reference clock to

which all audio data processing is synchronised. This clock is often referred to as the audio system’s

Master Clock. The WM8776 uses separate master clocks for the ADC and DAC. The external master

system clocks can be applied directly through the ADCMCLK and DACMCLK input pins with no

software configuration necessary. In a system where there are a number of possible sources for the

reference clock it is recommended that the clock source with the lowest jitter be used to optimise the

performance of the ADC and DAC.

The master clock for WM8776 supports DAC and ADC audio sampling rates from 256fs to 768fs,

where fs is the audio sampling frequency (DACLRC or ADCLRC) typically 32kHz, 44.1kHz, 48kHz or

96kHz (the DAC also supports operation at 128fs and 192fs and 192kHz sample rate). The master

clock is used to operate the digital filters and the noise shaping circuits.

In Slave mode the WM8776 has a master detection circuit that automatically determines the

relationship between the master clock frequency and the sampling rate (to within +/- 32 system

clocks). If there is a greater than 32 clocks error the interface is disabled and maintains the output

level at the last sample. The master clock should be synchronised with ADCLRC/DACLRC for optical

performance, although the WM8776 is tolerant of phase variations or jitter on this clock. Table 6

shows the typical master clock frequency inputs for the WM8776.

The signal processing for the WM8776 typically operates at an oversampling rate of 128fs for both

ADC and DAC. The exception to this for the DAC is for operation with a 128/192fs system clock, e.g.

for 192kHz operation where the oversampling rate is 64fs. For ADC operation at 96kHz it is

recommended that the user set the ADCOSR bit. This changes the ADC signal processing

oversample rate to 64fs.

System Clock Frequency (MHz)

128fs

192fs

SAMPLING

RATE

(DACLRC/

ADCLRC)

DAC ONLY

256fs

384fs

512fs

768fs

32kHz

4.096

6.144

8.192

12.288

16.384

24.576

44.1kHz

5.6448

8.467

11.2896

16.9340

22.5792

33.8688

48kHz

6.144

9.216

12.288

18.432

24.576

36.864

96kHz

12.288

18.432

24.576

36.864

Unavailable

192kHz

24.576

36.864

Unavailable Unavailable Unavailable

Unavailable

Table 6 System Clock Frequencies Versus Sampling Rate

In Master mode DACBCLK, ADCBCLK, DACLRC and ADCLRC are generated by the WM8776. The

frequencies of ADCLRC and DACLRC are set by setting the required ratio of DACMCLK to DACLRC

and ADCMCLK to ADCLRC using the DACRATE and ADCRATE control bits (Table 7).

ADCRATE[2:0]/

DACRATE[2:0]

ADCMCLK/DACMCLK:

ADCLRC/DACLRC

RATIO

000

128fs (DAC Only)

001

192fs (DAC Only)

010

256fs

011

384fs

100

512fs

101

768fs

Table 7 Master Mode MCLK:ADCLRC/DACLRC Ratio Select

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