8.3.3 Device Digital Logic Control

The TMUX9616 is controlled by a SPI interface to a 16-bit shift register, and a CLR pin. The SPI interface can

run at speeds up to 72 MHz. It can also be run with 1.8 V – 5 V logic levels (set by logic supply VLL). The DIN

pin will take in the data for the 16-bit register, and CLK will take in the clock signal. Data is shifted in on the DIN

pin with the most-significant bit (MSB) first. After writing in 16 bits into the shift register using DIN and CLK, LE is

then used to latch the state of the switches in the shift register to change the state of the switches in analog. The

switches go to a state of retaining their present state on the rising edge of the LE pin. When LE is high, updates

to the shift register does not change the condition of the 16 switches until LE is made low again. When LE is low,

the shift register data flows through the latch and the condition of the 16 switches will be changed as the shift

register is updated.

TMUX9616 16-bit shift register can be used in daisy chain mode. This is done by connecting the DOUT pin

of the first TMUX9616 device to the DIN pin of the next TMUX9616 device in the chain. All TMUX9616 in the

daisy chain will share the same source CLK signal (the CLK pin of each device in the daisy chain will be shorted

together). DOUT is the data output pin of the 16th bit of the shift register, which is the data on DIN clock shifted

by 16 clock cycles. The LE pin of each device in the chain will be shorted together, using the same LE source.

Assuming N number of TMUX9616 devices in the daisy chain, the standard method of writing to the shift

registers is to write 16 * N bits of data, corresponding to each switch in the daisy chain, with LE set high. Once

all 16 * N bits are written into the shift register, LE is pulsed low for at least tWLE to update the condition of the

16 * N switches in the daisy chain to the new state recorded in the shift register. Then LE is set high again so

that the state of the switches will not change until the next 16 * N bits are written into the shift register (and LE is

pulsed low again following the 16 * N bit write).

The CLR pin, when asserted high, causes all the 16 switches in TMUX9616 to turn OFF, regardless of the state

of the bits in the 16-bit shift register. When the CLR pin asserted low, the switches will then use the shift register

again to set its values.

For more details on programming the shift register and the logic state of each switch, see the Device Logic

Table section. For more details of programming the shift register with the correct digital timings, see the Timing

Diagrams section and the Digital Timings table. For more details on the maximum speeds obtainable in daisy

chain mode depending on device configuration, see the Switching Characteristics table. Figure 8-1 shows more

details on how to connect the TMUX9616 device's in daisy chain mode.

DIN

CLK

DOUT

Sx

Dx

CMOS SPI

Pulsar

PZT

DOUT

Sx

Dx

Pulsar

PZT

DOUT

Sx

Dx

Pulsar

PZT

N.C.

Pulsar w/

TR Switch

Central

FPGA

Digital

Power

Supply

VLL

CMOS SPI

System/Console

Probe Head

Probe

Cable

Probe

Connector

CMOS SPI

CMOS SPI

/LE

DIN

CLK

/LE

DIN

CLK

/LE

Figure 8-1. Daisy Chain System Block Diagram

TMUX9616

SCDS436 – SEPTEMBER 2023

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