8.3.4 Latch-Up Immunity by Device Construction

Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition

is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains

even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic

damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the

low impedance path.

The TMUX9616 is constructed on silicon on insulator (SOI) based process where an oxide layer is added

between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures from forming. The

oxide layer is also known as an insulating trench and prevents triggering of latch up events due to overvoltage,

fast voltage slew rates, and current injections. The latch-up immunity feature allows the TMUX9616 to be used in

harsh environments. For more information on latch-up immunity, refer to Using Latch Up Immune Multiplexers to

Help Improve System Reliability.

8.4 Device Functional Modes

8.4.1 Normal Mode

In normal mode operation, TMUX9616 is controlled by its digital logic, which is detailed in the Device Digital

Logic Control section. In normal mode, switches are available to be used to pass high voltage ±110 V signals

(signals from VSS to VDD). More details of the device operation in normal mode can be found in the Feature

Description and Device Logic Table sections.

8.4.2 Device Power Up

TMUX9616 will be powered up once VLL, VDD, and VSS reach their final voltage. VLL, VDD, and VSS can be

powered up in any order (there is no power sequencing requirement). The device digital logic control will not

receive updates until both VLL, VDD, and VSS are powered up. Additionally, after VLL, VDD, and VSS are powered

up, the system FPGA or controller should wait at least 500 μs until writing to the device digital logic control. For

more details on the device digital logic control, see the Device Digital Logic Control section.

On power-up, all 16 switches in TMUX9616 will be in the OFF state.

8.5 Device Logic Table

Table 8-1. Device Logic Table(1)(2)(3)(4)(5)(6)(7)

Inputs

Outputs

D0

D1

...

D15

LE

CLR

SW0

SW1

...

SW15

0

—

...

—

L

L

OFF

—

...

—

1

—

—

L

L

ON

—

—

—

0

—

L

L

—

OFF

—

—

1

—

L

L

—

ON

—

—

—

—

L

L

—

—

—

—

—

—

L

L

—

—

—

—

—

0

L

L

—

—

OFF

—

—

1

L

L

—

—

ON

X

X

X

X

H

L

HOLD PREVIOUS STATE

X

X

X

X

X

H

OFF

OFF

OFF

OFF

(1)

All 16 switches operate independently.

(2)

Serial data is clocked in on the rising edge of CLK. Data is shifted in on the DIN pin with the most-significant bit (MSB) first.

(3)

The switches go to a state of retaining their present state on the rising edge of the LE pin. Once the LE pin is high, updates to the shift

register no longer change the condition of the 16 switches until the LE pin is made low again. When the LE is low, the shift register

data flows through the latch.

(4)

Shift register clocking has no effect on the switch states if the LE pin is high.

(5)

DOUT is the data output pin of the 16 bit shift register for daisy chaining multiple muxes together. It is the data of the DIN clock shifted

by the 16 clock cycles.

(6)

The CLR input overrides all other inputs.

(7)

While LE = H or CLR = H, if the CLK pin still receiving a valid clock signal, DIN will still function and input data into the shift register,

and DOUT will still output the contents on the shift register. However, while LE = H or CLR = H, the state of the analog switches is no

longer dependent on the contents of the shift register, but rather takes the state per this logic table.

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TMUX9616

SCDS436 – SEPTEMBER 2023

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