AT32AP7002 datasheet(25/45 Pages) ATMEL

25 / 45 page

32054AS–AVR32–02/07

AT32AP7002

7.7

Peripheral Multiplexing on IO lines

The AT32AP7002 features five PIO controllers, PIOA to PIOE, that multiplex the I/O lines of the

peripheral set. Each PIO Controller controls up to thirty-two lines.

Each line can be assigned to one of two peripheral functions, A or B. The tables in the following

pages define how the I/O lines of the peripherals A and B are multiplexed on the PIO

Controllers.

Note that some output only peripheral functions might be duplicated within the tables.

7.7.1

PIO Controller A Multiplexing

Table 7-9.

PIO Controller A Multiplexing

I/O Line

Peripheral A

Peripheral B

PA00

SPI0 - MISO

SSC1 - RX_FRAME_SYNC

PA01

SPI0 - MOSI

SSC1 - TX_FRAME_SYNC

PA02

SPI0 - SCK

SSC1 - TX_CLOCK

PA03

SPI0 - NPCS[0]

SSC1 - RX_CLOCK

PA04

SPI0 - NPCS[1]

SSC1 - TX_DATA

PA05

SPI0 - NPCS[2]

SSC1 - RX_DATA

PA06

TWI - SDA

USART0 - RTS

PA07

TWI - SCL

USART0 - CTS

PA08

PSIF - CLOCK

USART0 - RXD

PA09

PSIF - DATA

USART0 - TXD

PA10

MCI - CLK

USART0 - CLK

PA11

MCI - CMD

TC0 - CLK0

PA12

MCI - DATA[0]

TC0 - A0

PA13

MCI - DATA[1]

TC0 - A1

PA14

MCI - DATA[2]

TC0 - A2

PA15

MCI - DATA[3]

TC0 - B0

PA16

USART1 - CLK

TC0 - B1

PA17

USART1 - RXD

TC0 - B2

PA18

USART1 - TXD

TC0 - CLK2

PA19

USART1 - RTS

TC0 - CLK1

PA20

USART1 - CTS

SPI0 - NPCS[3]

PA21

SSC0 - RX_FRAME_SYNC

PWM - PWM[2]

PA22

SSC0 - RX_CLOCK

PWM - PWM[3]

PA23

SSC0 - TX_CLOCK

TC1 - A0

PA24

SSC0 - TX_FRAME_SYNC

TC1 - A1

PA25

SSC0 - TX_DATA

TC1 - B0

PA26

SSC0 - RX_DATA

TC1 - B1

PA27

SPI1 - NPCS[3]

TC1 - CLK0

PA28

PWM - PWM[0]

TC1 - A2

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