AT32AP7002 datasheet(37/45 Pages) ATMEL

37 / 45 page

32054AS–AVR32–02/07

AT32AP7002

Boot Sequence

This chapter summarizes the boot sequence of the AT32AP7002. The behaviour after power-up

is controlled by the Power Manager.

8.1

Starting of clocks

After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the

power has stabilized throughout the device. Once the power has stabilized, the device will use

the XIN0 pin as clock source. XIN0 can be connected either to an external clock, or a crystal.

The OSCEN_N pin is connected either to VDD or GND to inform the Power Manager on how the

XIN0 pin is connected. If XIN0 receives a signal from a crystal, dedicated circuitry in the Power

Manager keeps the part in a reset state until the oscillator connected to XIN0 has settled. If XIN0

receives an external clock, no such settling delay is applied.

On system start-up, the PLLs are disabled. All clocks to all modules are running. No clocks have

a divided frequency, all parts of the system recieves a clock with the same frequency as the

XIN0 clock.

8.2

Fetching of initial instructions

After reset has been released, the AVR32AP CPU starts fetching instructions from the reset

address, which is 0xA000_0000. This address lies in the P2 segment, which is non-translated,

non-cacheable, and permanently mapped to the physical address range 0x0000_0000 to

0x2000_0000. This means that the instruction being fetched from virtual address 0xA000_0000

is being fetched from physical address 0x0000_0000. Physical address 0x0000_0000 is

mapped to EBI SRAM CS0. This is the external memory the device boots from.

The code read from the SRAM CS0 memory is free to configure the system to use for example

the PLLs, to divide the frequency of the clock routed to some of the peripherals, and to gate the

clocks to unused peripherals.

AT32AP7002 Datasheet(PDF) 37 Page - ATMEL Corporation