AT32AP7002 datasheet(39/45 Pages) ATMEL

39 / 45 page

32054AS–AVR32–02/07

AT32AP7002

10. Errata

10.1

Rev. C

SPI FDIV option does not work

Selecting clock signal using FDIV = 1 does not work as specified.

Fix/Workaround

Do not set FDIV = 1.

SPI Chip Select 0 BITS field overrides other Chip Selects

The BITS field for Chip Select 0 overrides BITS fields for other Chip selects.

Fix/Workaround

Update Chip Select 0 BITS field to the relevant settings before transmitting with Chip Selects

other than 0.

SPI LASTXFER may be overwritten

When Peripheral Select (PS) = 0, the LASTXFER-bit in the Transmit Data Register (TDR)

should be internally discared. This fails and may cause problems during DMA transfers.

Transmitting data using the PDC when PS=0, the size of the transferred data is 8- or 16-bits.

The upper 16 bits of the TDR will be written to a random value. If Chip Select Active After

Transfer (CSAAT) = 1, the behavior of the Chip Select will be unpredictable.

Fix/Workaround

- Do not use CSAAT = 1 if PS = 0

- Use GPIO to control Chip Select lines

- Select PS=1 and store data for PCS and LASTXFER for each data in transmit buffer.

SPI LASTXFER overrides Chip Select

The LASTXFER bit overrides Chip Select input when PS = 0 and CSAAT is used.

Fix/Workaround

- Do not use the CSAAT

- Use GPIO as Chip Select input

- Select PS = 1. Transfer 32-bit with correct LASTXFER settings.

MMC data drite operation with less than 12 bytes is impossible.

The Data Write operation with a number of bytes less than 12 is impossible

Fix/Workaround

The PDC counters must always be equal to 12 bytes for data transfers lower than 12 bytes.

The BLKLEN or BCNT field are used to specify the real count number.

MMC SDIO interrupt only works for slot A

If 1-bit data bus width and on other slots than slot A, the SDIO interrupt can not be cap-

tured.

Fix/Workaround

Use slot A.

AT32AP7002 Datasheet(PDF) 39 Page - ATMEL Corporation