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AT25128 Datasheet(PDF) 1 Page - ATMEL Corporation |
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AT25128 Datasheet(HTML) 1 Page - ATMEL Corporation |
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1 / 22 page ![]() 1 8-lead SOIC 1 2 3 4 8 7 6 5 CS SO WP GND VCC HOLD SCK SI Features • Serial Peripheral Interface (SPI) Compatible • Supports SPI Modes 0 (0,0) and 3 (1,1) • Low-voltage and Standard-voltage Operation – 2.7 (V CC = 2.7V to 5.5V) – 1.8 (V CC = 1.8V to 5.5V) • 3 MHz Clock Rate • 64-byte Page Mode and Byte Write Operation • Block Write Protection – Protect 1/4, 1/2, or Entire Array • Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection • Self-timed Write Cycle (5 ms Typical) • High-reliability – Endurance: 100,000 Write Cycles – Data Retention: >200 Years • Automotive Grade, Extended Temperature and Lead-Free Devices Available • 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead and 16-lead JEDEC SOIC, 14-lead and 20-lead TSSOP, and 8-lead Leadless Array Packages Description The AT25128/256 provides 131,072/262,144 bits of serial electrically-erasable pro- grammable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space saving 8-lead PDIP (AT25128/256), 8-lead EIAJ SOIC (AT25128/256), 8-lead and 16-lead JEDEC SOIC (AT25128), 14-lead TSSOP (AT25128), 20-lead TSSOP (AT25128/256), and 8-lead Leadless Array (AT25256) packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions. Table 1. Pin Configuration Pin Name Function CS Chip Select SCK Serial Data Clock SI Serial Data Input SO Serial Data Output GND Ground VCC Power Supply WP Write Protect HOLD Suspends Serial Input NC No Connect DC Don't Connect Rev. 0872O–SEEPR–03/05 *Note: Pins 3, 4 and 17, 18 are internally connected for 14-lead TSSOP socket compatibility. SPI Serial EEPROMs 128K (16,384 x 8) 256K (32,768 x 8) AT25128(1) AT25256(2) Notes: 1. This device is not rec- ommended for new designs. Please refer to AT25128A. 2. This device is not rec- ommended for new designs. Please refer to AT25256A. 20-lead TSSOP* 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 NC CS SO SO NC NC WP GND DC NC NC VCC HOLD HOLD NC NC SCK SI DC NC 8-lead PDIP 1 2 3 4 8 7 6 5 CS SO WP GND VCC HOLD SCK SI 16-lead SOIC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CS SO NC NC NC NC WP GND VCC HOLD NC NC NC NC SCK SI 14-lead TSSOP 1 2 3 4 5 6 7 14 13 12 11 10 9 8 CS SO NC NC NC WP GND VCC HOLD NC NC NC SCK SI 8-lead Leadless Array Bottom View 1 2 3 4 8 7 6 5 VCC HOLD SCK SI CS SO WP GND |
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