9.4 Layout

9.4.1 Layout Guidelines

Attention to good layout practices is always recommended. For best operational performance of the device, use

the following PCB layout practices:

• Make sure that both input paths are well-matched for source impedance and capacitance to avoid converting

common-mode signals into differential signals.

• Use bypass capacitors to reduce the coupled noise by providing low-impedance power sources local to the

analog circuitry.

– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

• Route the input traces as far away from the supply or output traces as possible to reduce parasitic coupling. If

these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than crossing

in parallel with the noisy trace.

• Place the external components as close to the device as possible.

• Keep the traces as short as possible.

9.4.2 Layout Example

Use ground pours for

shielding the input

signal pairs

1

GS

8

SHDN

2

–IN

7

VS+

3

+IN

6

OUT

4

VS

5

REF

R1

R2

C1

C2

GND

GND

+V

–IN

+IN

OUT

Input traces routed

adjacent to each other

–

V

Ground plane

removed at gain

resistor to minimize

parasitic capacitance

Low-impedance

connection for

reference terminal

Place bypass

capacitors as close to

IC as possible

+IN

–IN

+V

OUT

–V

R1

R2

C1

C2

INA351ABS

GND

_____

Figure 9-7. Example Schematic and Associated PCB Layout

INA351

SBOSAD5C – DECEMBER 2022 – REVISED MAY 2023

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