10 Layout

10.1 Layout Guidelines

Comparators are very sensitive to input noise. For best results, adhere to the following layout guidelines.

1. Use a printed-circuit-board (PCB) with a good, unbroken, low-inductance ground plane. Proper grounding

(use of a ground plane) helps maintain specified device performance and input/output trace impedances.

2. To minimize supply noise, place a decoupling capacitor (0.1-μF ceramic, surface-mount capacitor) directly

between VCCI/VCCO and VEE.

3. On the inputs and outputs, utilize matched trace lengths to minimize timing skew. Also, minimize

trace lengths and maximize ground pour spacings around the input and output traces to limit parasitic

capacitance.

4. Solder the device directly to the PCB rather than using a socket.

5. For slow-moving input signals, take care to prevent parasitic feedback. A small capacitor (1000 pF or less)

placed between the inputs can help eliminate oscillations in the transition region. This capacitor causes

minimal degradation to propagation delay when source impedance is low.

6. Use a 100 Ω termination resistor across the device's LVDS outputs.

7. Use higher performance substrate materials such as Rogers or High-Speed FR4.

8. PCB signal layers from the TLV3604EVM are shown for reference.

10.2 Layout Example

Figure 10-1 shows the 4 layer PCB signal routing for the TLV3604EVM as an example for how layout on this

device can be done.

TLV3604, TLV3605, TLV3607

SNOSDA2E – AUGUST 2020 – REVISED JULY 2023

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