AT43USB325 datasheet(28/109 Pages) ATMEL

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3355C–USB–4/05

AT43USB325

$005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is

set in the TIFR.

• Bit 4 – Res: Reserved Bit

This bit is a reserved bit in the AT43USB325 and always reads zero.

• Bit 3 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable

When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector

$003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is

set in the TIFR.

• Bit 2 – Res: Reserved Bit

This bit is a reserved bit in the AT43USB325 and always reads zero.

• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $007) is

executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the TIFR.

• Bit 0 – Res: Reserved Bit

This bit is a reserved bit in the AT43USB325 and always reads zero.

4.9.4

Timer/Counter Interrupt Flag Register – TIFR

• Bit 7 – TOV1: Timer/Counter1 Overflow Flag

The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by the hard-

ware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared

by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow

Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In

PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.

• Bit 6 – OCF1A: Output Compare Flag 1A

The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the

data in OCR1A - Output Compare Register 1A. OCF1A is cleared by the hardware when execut-

ing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a

logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match

InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Inter-

rupt is executed.

• Bit 5 – OCF1B: Output Compare Flag 1B

The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the

data in OCR1B - Output Compare Register 1B. OCF1B is cleared by the hardware when execut-

Bit

210

$38 ($58)

TOV1

OCF1A

OCIFB

–

ICF1

–

TOV0

–

TIFR

Read/Write

R/W

Initial Value

AT43USB325 Datasheet(PDF) 28 Page - ATMEL Corporation

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