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AT89LP213 Datasheet(PDF) 75 Page - ATMEL Corporation |
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AT89LP213 Datasheet(HTML) 75 Page - ATMEL Corporation |
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75 / 90 page ![]() 75 3538A–MICRO–7/06 AT89LP213/214 [Preliminary] 23.8.6 Timing Parameters The timing parameters for Figure 23-5, Figure 23-6, Figure 23-7, Figure 23-8, and Figure 23-10 are shown in Table 23-6. Table 23-6. Programming Interface Timing Parameters Note: 1. t SCK is independent of tCLCL. Symbol Parameter Min Max Units tCLCL System Clock Cycle Time 0 60 ns tPWRUP Power On to SS High Time 10 µs tPOR Power-on Reset Time 100 µs tPWRDN SS Tristate to Power Off 1 µs tRLZ RST Low to I/O Tristate tCLCL 2 tCLCL ns tSTL RST Low Settling Time 100 ns tRHZ RST High to SS Tristate 0 2 tCLCL ns tSCK Serial Clock Cycle Time 200(1) ns tSHSL Clock High Time 75 ns tSLSH Clock Low Time 50 ns tSR Rise Time 25 ns tSF Fall Time 25 ns t SIS Serial Input Setup Time 10 ns t SIH Serial Input Hold Time 10 ns t SOH Serial Output Hold Time 10 ns t SOV Serial Output Valid Time 35 ns t SOE Output Enable Time 10 ns t SOX Output Disable Time 25 ns t SSE SS Enable Lead Time t SLSH ns t SSD SS Disable Lag Time t SLSH ns t ZSS SCK Setup to SS Low 25 ns t SSZ SCK Hold after SS High 25 ns t WR Write Cycle Time 2.5 ms t AWR Write Cycle with Auto-Erase Time 5 ms t ERS Chip Erase Cycle Time 7.5 ms |
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