AT89LP213 datasheet(17/90 Pages) ATMEL

17 / 90 page

3538A–MICRO–7/06

AT89LP213/214 [Preliminary]

begin. The time-out period is controlled by the Start-up Timer Fuses (see Table 10-1 on page

15). The interrupt pin need not remain low for the entire time-out period.

Figure 11-1. Interrupt Recovery from Power-down (PWDEX = 0)

When PWDEX = “1”, the wake-up period is controlled externally by the interrupt. Again, at the

falling edge on the interrupt pin, power-down is exited and the oscillator is restarted. However,

the internal clock will not propagate until the rising edge of the interrupt pin as shown in Figure

11-2. The interrupt pin should be held low long enough for the selected clock source to stabilize.

After the rising edge on the pin the interrupt service routine will be executed.

Figure 11-2. Interrupt Recovery from Power-down (PWDEX = 1)

11.2.2

Reset Recovery from Power-down

The wake-up from Power-down through an external reset is similar to the interrupt with

PWDEX = “0”. At the falling edge of RST, Power-down is exited, the oscillator is restarted, and

an internal timer begins counting as shown in Figure 11-3. The internal clock will not be allowed

to propagate to the CPU until after the timer has timed out. The time-out period is controlled by

the Start-up Timer Fuses. (See Table 10-1 on page 15). If RST returns high before the time-out,

a two clock cycle internal reset is generated when the internal clock restarts. Otherwise the

device will remain in reset until RST is brought high.

PWD

INT1

XTAL1

tSUT

INTERNAL

CLOCK

PWD

INT1

XTAL1

INTERNAL

CLOCK

AT89LP213 Datasheet(PDF) 17 Page - ATMEL Corporation