AT89LP213 datasheet(18/90 Pages) ATMEL

18 / 90 page

3538A–MICRO–7/06

AT89LP213/214 [Preliminary]

Figure 11-3. Reset Recovery from Power-down.

12. Interrupts

The AT89LP213/214 provides 7 interrupt sources: two external interrupts, two timer interrupts, a

serial port interrupt, a general-purpose interrupt, and an analog comparator interrupt. These

interrupts and the system reset each have a separate program vector at the start of the program

memory space. Each interrupt source can be individually enabled or disabled by setting or clear-

ing a bit in the interrupt enable register IE. The IE register also contains a global disable bit, EA,

which disables all interrupts.

Each interrupt source (except the analog comparator) can be individually programmed to one of

four priority levels by setting or clearing bits in the interrupt priority registers IP and IPH. The

analog comparator is fixed at the lowest priority level. An interrupt service routine in progress

can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower

priority. The highest priority interrupt cannot be interrupted by any other interrupt source. If two

requests of different priority levels are pending at the end of an instruction, the request of higher

priority level is serviced. If requests of the same priority level are pending at the end of an

Table 11-1.

PCON

– Power Control Register

PCON = 87H

Reset Value = 000X 0000B

Not Bit Addressable

SMOD1

SMOD0

PWDEX

POF

GF1

GF0

IDL

Bit

543

PWD

RST

XTAL1

tSUT

INTERNAL

CLOCK

INTERNAL

RESET

Symbol

Function

SMOD1

Double Baud Rate bit. Doubles the baud rate of the UART in Modes 1, 2, or 3.

SMOD0

Frame Error Select. When SMOD0 = 1, SCON.7 is SM0. When SMOD0 = 1, SCON.7 is FE. Note that FE will be set after

a frame error regardless of the state of SMOD0.

PWDEX

Power-down Exit Mode. When PWDEX = 1, wake up from Power-down is externally controlled. When PWDEX = 1, wake

up from Power-down is internally timed.

POF

Power Off Flag. POF is set to “1” during power up (i.e. cold reset). It can be set or reset under software control and is not

affected by RST or BOD (i.e. warm resets).

GF1, GF0

General-purpose Flags

Power-down bit. Setting this bit activates power-down operation.

IDL

Idle Mode bit. Setting this bit activates Idle mode operation

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