AT89LP213 datasheet(27/90 Pages) ATMEL

27 / 90 page

3538A–MICRO–7/06

AT89LP213/214 [Preliminary]

14. Enhanced Timer/Counters

The AT89LP213/214 has two 16-bit Timer/Counter registers: Timer 0 and Timer 1. As a Timer,

the register increase every clock cycle by default. Thus, the register counts clock cycles. Since a

clock cycle consists of one oscillator period, the count rate is equal to the oscillator frequency.

The timer rate can be prescaled by a value between 1 and 16 using the Timer Prescaler (see

Table 9-2 on page 13). Both Timers share the same prescaler.

As a Counter, the register is incremented in response to a l-to-0 transition at its corresponding

input pin, T0 or T1. The external input is sampled every clock cycle. When the samples show a

high in one cycle and a low in the next cycle, the count is incremented. The new count value

appears in the register during the cycle following the one in which the transition was detected.

Since 2 clock cycles are required to recognize a l-to-0 transition, the maximum count rate is 1/2

of the oscillator frequency. There are no restrictions on the duty cycle of the input signal, but it

should be held for at least one full clock cycle to ensure that a given level is sampled at least

once before it changes. In the AT89LP214, the T0 and T1 inputs are not available at the pins.

However, the inputs may be exercised in software by toggling the P3.4 and P3.5 bits in the

Port 3 register.

Furthermore, the Timer or Counter functions for Timer 0 and Timer 1 have four operating modes:

variable width timer, 16-bit auto-reload timer, 8-bit auto-reload timer, and split timer. The control

bits C/T in the Special Function Register TMOD select the Timer or Counter function. The bit

pairs (M1, M0) in TMOD select the operating modes.

14.1

Mode 0 – Variable Width Timer/Counter

Both Timers in Mode 0 are 8-bit Counters with a variable prescaler. The prescaler may vary from

1 to 8 bits depending on the PSC bits in TCONB, giving the timer a range of 9 to 16 bits.

By default the timer is configured as a 13-bit timer compatible to Mode 0 in the standard 8051.

Figure 14-1 shows the Mode 0 operation as it applies to Timer 1 in 13-bit mode. As the count

rolls over from all “1”s to all “0”s, it sets the Timer interrupt flag TF1. The counter input is enabled

to the Timer when TR1 = 1 and either GATE = 0 or INT1 = 1. Setting GATE = 1 allows the Timer

to be controlled by external input INT1, to facilitate pulse width measurements. TR1 is a control

bit in the Special Function Register TCON. GATE is in TMOD. The 13-bit register consists of all

8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate and should

be ignored. Setting the run flag (TR1) does not clear the registers.

Note:

RH1/RL1 are not required by Timer 1 during Mode 0 and may be used as temporary storage

registers.

Mode 0:

Time-out Period

256

PSC01

Oscillator Frequency

-------------------------------------------------------

TPS 1

()

AT89LP213 Datasheet(PDF) 27 Page - ATMEL Corporation

AT89LP213 Datasheet(HTML) 27 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

Datasheet Download

Link URL