AT26F004 datasheet(27/38 Pages) ATMEL

27 / 38 page

3588C–DFLASH–04/06

AT26F004

11.4

Hold

The HOLD pin is used to pause the serial communication with the device without having to stop

or reset the clock sequence. The Hold mode, however, does not have an affect on any internally

self-timed operations such as a program or erase cycle. Therefore, if an erase cycle is in

progress, asserting the HOLD pin will not pause the operation, and the erase cycle will continue

until it is finished.

The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated

simply by asserting the HOLD pin during the SCK low pulse. If the HOLD pin is asserted during

the SCK high pulse, then the Hold mode won't be started until the beginning of the next SCK low

pulse. The device will remain in the Hold mode as long as the HOLD pin and CS pin are

asserted.

While in the Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin

and the SCK pin will be ignored. The WP pin, however, can still be asserted or deasserted while

in the Hold mode.

To end the Hold mode and resume serial communication, the HOLD pin must be deasserted

during the SCK low pulse. If the HOLD pin is deasserted during the SCK high pulse, then the

Hold mode won't end until the beginning of the next SCK low pulse.

If the CS pin is deasserted while the HOLD pin is still asserted, then the Hold mode will abort

and the device may abort the current operation depending on whether or not a complete

opcode, address bytes, or data byte was already clocked into the device before the Hold mode

was entered. The WEL bit in the Status Register will be reset back to a logical “0” if a program,

erase, Protect Sector, Unprotect Sector, or Write Status Register operation aborts as a result of

the Hold mode aborting.

Figure 11-4. Hold Mode

SCK

HOLD

Hold

AT26F004 Datasheet(PDF) 27 Page - ATMEL Corporation