AAT2805 datasheet(13/16 Pages) AAT

13 / 16 page

Table 4: Maximum Current Settings Address 4.

Disabled Current Sinks

The backlight charge pump is equipped with an auto-

disable feature to protect against an LED failure con-

dition. Current sink inputs that are not used should

be disabled.

To disable and properly terminate

unused current sink inputs, they must be tied to VOUT.

If left unconnected or terminated to ground, the part

will be forced to operate in 2X charge pump mode.

Properly terminating unused current sink inputs is

important to prevent the charge pump modes from

activating prematurely. When properly terminated,

only a small sense current flows for each disabled

channel. The sense current for each disabled chan-

nel is less than 120µA.

Applications Information

LED Selection

The AAT2805 is specifically intended for driving white

LEDs. However, the device design will allow the

AAT2805 to drive most types of LEDs with forward

voltage specifications ranging from 2.0V to 4.3V.

LED applications may include main display back-

lighting, camera photo-flash applications, color

(RGB) LEDs, infrared (IR) diodes for remotes, and

other loads benefiting from a controlled output cur-

rent generated from a varying input voltage. Since

the D1 to D4 input current sinks are matched with

negligible voltage dependence, the LED brightness

will be matched regardless of the specific LED for-

ward voltage (VF) levels.

In some instances (e.g., in high-luminous-output

applications such as photo flash), it may be neces-

sary to drive high-VF type LEDs. The low dropout cur-

rent sinks in the AAT2805 make it capable of driving

LEDs with forward voltages as high as 4.3V at full

current from an input supply as low as 3.0V. Outputs

can be paralleled to drive high-current LEDs without

complication.

Data

Max Current

20mA Max Scale

30mA Max Scale

15mA Max Scale

Low Current Mode

AAT2805

Dual High Efficiency Charge Pump

for White LED and Flash Applications

2805.2006.04.1.7

AS2Cwire Serial Interface Timing Diagram

Address

Data

EN/SET

Address

Data Reg 1

Data Reg 2

2 . . .

n <= 16

THI

TLO

TLAT

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