VCC

P0 to P7

Configuration

Register

Decoder

PMOS_EN0

PMOS_EN1

PMOS_EN2

PMOS_EN3

NMOS_EN3

NMOS_EN2

NMOS_EN1

NMOS_EN0

Output Port

Register

Current Control

Register

PMOS_EN[3:0]

NMOS_EN[3:0]

Figure 7-3. Simplified output stage

Reducing the current drive capability may be desirable to reduce system noise. When the output switches there

is a peak current that is a function of the output drive selection. This peak current runs through the supply

and GND package inductance’s and creates a noise (some radiated, but more critically Simultaneous Switching

Noise (SSN)). In other words, switching many outputs at the same time will create ground and supply noise. The

output drive strength control through the Output Drive Strength registers allows the user to mitigate SSN issues

without the need of additional external components.

7.3.3 Interrupt Output (INT)

An interrupt is generated by any rising or falling edge of the port inputs in the input mode provided the interrupt

feature is unmasked. After time tiv, the INT signal is valid. Resetting the interrupt circuit is achieved when

data on the port is changed back to the original setting or when data is read from the port that generated the

interrupt. Resetting occurs in the read mode at the acknowledge (ACK) bit after the rising edge of the SCL

signal. Interrupts that occur during the ACK clock pulse can be lost (or be very short) due to the resetting of the

interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.

Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output

cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the

state of the pin does not match the contents of the input port register.

The INT output has an open-drain structure and requires an external pull-up resistor to VCC if the interrupt

feature is required; otherwise, it may be left floating.

7.3.4 Reset Input (RESET)

The RESET input can be asserted to initialize the system while keeping the VCC supply at its operating level.

A reset can be accomplished by holding the RESET pin low for a minimum of tW. The TCAL9538 registers and

I2C/SMBus state machine are changed to their default state once RESET is low (0). When RESET is high (1),

the I/O levels at the P port can be changed externally or through the controller. This input requires a pull-up

resistor to VCC, if no active connection is used. When RESET is toggled the input port register is updated to

reflect the state of the GPIO pins.

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TCAL9538

SCPS280A – NOVEMBER 2022 – REVISED NOVEMBER 2023

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Product Folder Links: TCAL9538