LAN91C96IQFP datasheet(49/109 Pages) SMSC

49 / 109 page

Non-PCI Single-Chip Full Duplex Ethernet Controller

SMSC DS – LAN91C96I

Page 49

Rev. 03-28-07

DATASHEET

I/O SPACE - BANK2

OFFSET

NAME

TYPE

SYMBOL

FIFO PORTS REGISTER

READ ONLY

FIFO

This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO.

The packet numbers to be processed by the interrupt service routines are read from this register.

REMPTY

RX FIFO PACKET NUMBER

TEMPTY

TX FIFO PACKET NUMBER

REMPTY - No receive packets queued in the RX FIFO. For polling purposes, uses the RCV_INT bit in the

Interrupt Status Register.

TOP OF RX FIFO PACKET NUMBER - Packet number presently at the output of the RX FIFO. Only valid

if REMPTY is clear. The packet is removed from the RX FIFO using MMU Commands 6) or 8).

TEMPTY - No transmit packets in completion queue. For polling purposes, uses the TX_INT bit in the

Interrupt Status Register.

TX FIFO PACKET NUMBER - Packet number presently at the output of the TX FIFO.

Only valid if

TEMPTY is clear. The packet is removed when a TX INT acknowledge is issued.

Note:

For software compatibility with future versions, the value read from each FIFO register is intended to be

written into the PNR as is, without masking higher bits (provided TEMPTY and REMPTY = 0 respectively).

I/O SPACE - BANK2

OFFSET

NAME

TYPE

SYMBOL

POINTER REGISTER

READ/WRITE

PTR

RCV

AUTO

INCR.

READ

ETEN

AutoTx

POINTER HIGH

POINTER LOW

POINTER REGISTER - The value of this register determines the address to be accessed within the

transmit or receive areas. It will auto-increment on accesses to the data register when AUTO INCR. is set.

The increment is by one for every byte access, and by two for every word access. When RCV is set the

address refers to the receive area and uses the output of RX FIFO as the packet number, when RCV is

clear the address refers to the transmit area and uses the packet number at the Packet Number Register.

READ bit - Determines the type of access to follow. If the READ bit is high the operation intended is a

read. If the READ bit is low the operation is a write. Loading a new pointer value, with the READ bit high,

generates a pre-fetch into the Data Register for read purposes.

Read-back of the pointer will indicate the value of the address last accessed by the CPU (rather than the

last pre-fetched). This allows any interrupt routine that uses the pointer, to save it and restore it without

affecting the process being interrupted.

The Pointer Register should not be loaded until 400ns after the last write operation to the Data Register to

ensure that the Data Register FIFO is empty. On reads, if IOCHRDY is not connected to the host, the Data

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