LAN91C96IQFP datasheet(65/109 Pages) SMSC

65 / 109 page

Non-PCI Single-Chip Full Duplex Ethernet Controller

SMSC DS – LAN91C96I

Page 65

Rev. 03-28-07

DATASHEET

TX Interrupt With AUTO_RELEASE = FALSE

Save the Packet Number Register

Saved_PNR = Read Byte (Bank 2, Offset 2)

Read the EPH Status Register

Temp = Read (Bank 0, Offset 2)

Acknowledge TX Interrupt

Write Byte (0x02, (Bank 2, Offset C));

Check for Status of Transmission

If ( Temp AND 0x0001)

{

//If Successful Transmission

Step 4.1.1: Issue MMU Release (Release Specific Packet)

Write (0x00A0, (Bank2, Offset 0));

Step 4.1.2: Return from the routine

}

else

{

//Transmission has FAILED

// Now we can either release or re-enqueue the packet

Step 4.2.1: Get the packet to release/re-enqueue, stored in FIFO

Temp = Read (Bank 2, Offset 4)

Temp = Temp & 0x003F

Step 4.2.2: Write to the PNR

Write (Temp, (Bank2, Offset 2))

Step 4.2.3

// Option 1: Release the packet

Write (0x00A0, (Bank2, Offset 0));

//Option 2: Re-Enqueue the packet

Write (0x00C0, (Bank2, Offset 0));

Step 4.2.4: Re-Enable Transmission

Temp = Read(Bank0, Offset 0);

Temp = Temp2 OR 0x0001

Write (Temp2, (Bank 0, Offset 0));

Step 4.2.5: Return from the routine

}

Restore the Packet Number Register

Write Byte (Saved_PNR, (Bank 2, Offset 2))

Figure 8.3 – TX INTR

LAN91C96IQFP Datasheet(PDF) 65 Page - SMSC Corporation

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