AD9236 datasheet(17/36 Pages) AD

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AD9236

Rev. B | Page 17 of 36

TIMING

In all reference configurations, REFT and REFB drive the A/D

conversion core and establish its input span. The input range of

the ADC always equals twice the voltage at the reference pin for

either an internal or an external reference.

The AD9236 provides latched data outputs with a pipeline delay

of seven clock cycles. Data outputs are available one propagation

delay (tPD) after the rising edge of the clock signal. Refer to

Figure 2 for a detailed timing diagram.

03066-A-017

μF

0.1

μF

VREF

SENSE

0.5V

AD9236

VIN–

VIN+

REFT

0.1

μF

0.1

μF

0.1

μF

REFB

SELECT

LOGIC

ADC

CORE

The length of the output data lines and the loads placed on

them should be minimized to reduce transients within the

AD9236. These transients can degrade the converter’s dynamic

performance.

The lowest typical conversion rate of the AD9236 is 1 MSPS. At

clock rates below 1 MSPS, dynamic performance can degrade.

VOLTAGE REFERENCE

A stable and accurate 0.5 V voltage reference is built into the

AD9236. The input range can be adjusted by varying the

reference voltage applied to the AD9236 using either the

internal reference or an externally applied reference voltage.

The input span of the ADC tracks reference voltage changes

linearly. The various reference modes are summarized in Table 10

and described in the following sections.

Figure 33. Internal Reference Configuration

If the ADC is being driven differentially through a transformer,

the reference voltage can be used to bias the center tap

(common-mode voltage).

03066-0-018

μF

0.1

μF

VREF

SENSE

0.5V

AD9236

VIN–

VIN+

REFT

0.1

μF

0.1

μF

0.1

μF

REFB

SELECT

LOGIC

ADC

CORE

Internal Reference Connection

A comparator within the AD9236 detects the potential at the

SENSE pin and configures the reference into four possible

states, which are summarized in Table 10. If SENSE is

grounded, the reference amplifier switch is connected to the

internal resistor divider (see Figure 33), setting VREF to 1 V.

Connecting the SENSE pin to VREF switches the reference

amplifier output to the SENSE pin, completing the loop and

providing a 0.5 V reference output. If a resistor divider is

connected as shown in Figure 34, the switch is again set to the

SENSE pin. This puts the reference amplifier in a noninverting

mode with the VREF output defined as follows:

⎟

⎠

⎞

⎜

⎝

⎛ +

VREF

Figure 34. Programmable Reference Configuration

Table 10. Reference Configuration Summary

Selected Mode

SENSE Voltage

Resulting VREF (V)

Resulting Differential Span (V p-p)

External Reference

AVDD

N/A

2 × External Reference

Internal Fixed Reference

VREF

0.5

1.0

Programmable Reference

0.2 V to VREF

⎟

⎠

⎞

⎜

⎝

⎛ +

(See Figure 34)

2 × VREF

Internal Fixed Reference

AGND to 0.2 V

1.0

2.0

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