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LAN8187 Datasheet(PDF) 45 Page - SMSC Corporation

Part # LAN8187
Description  짹15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWRTM
PDF  72 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

LAN8187 Datasheet(HTML) 45 Page - SMSC Corporation

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±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWRTM
Datasheet
SMSC LAN8187/LAN8187I
45
Revision 1.0 (12-14-06)
DATASHEET
Table 5.36 Register 6 - Auto Negotiation Expansion
ADDRESS
NAME
DESCRIPTION
MODE
DEFAULT
6.15:5
Reserved
RO
0
6.4
Parallel Detection
Fault
1 = fault detected by parallel detection logic
0 = no fault detected by parallel detection logic
RO/
LH
0
6.3
Link Partner Next
Page Able
1 = link partner has next page ability
0 = link partner does not have next page ability
RO
0
6.2
Next Page Able
1 = local device has next page ability
0 = local device does not have next page ability
RO
0
6.1
Page Received
1 = new page received
0 = new page not yet received
RO/
LH
0
6.0
Link Partner Auto-
Negotiation Able
1 = link partner has auto-negotiation ability
0 = link partner does not have auto-negotiation ability
RO
0
Table 5.37 Register 16 - Silicon Revision
ADDRESS
NAME
DESCRIPTION
MODE
DEFAULT
16.15:10
Reserved
RO
0
16.9:6
Silicon Revision
Four-bit silicon revision identifier.
RO
0001
16.5:0
Reserved
RO
0
Table 5.38 Register 17 - Mode Control/Status
ADDRESS
NAME
DESCRIPTION
MODE
DEFAULT
17.15:14
Reserved
Write as 0; ignore on read.
RW
0
17.13
EDPWRDOWN
Enable the Energy Detect Power-Down mode:
0 = Energy Detect Power-Down is disabled
1 = Energy Detect Power-Down is enabled
RW
0
17.12
Reserved
Write as 0, ignore on read
RW
0
17.11
LOWSQEN
The Low_Squelch signal is equal to LOWSQEN AND
EDPWRDOWN.
Low_Squelch = 1 implies a lower threshold
(more sensitive).
Low_Squelch = 0 implies a higher threshold
(less sensitive).
RW
0
17.10
MDPREBP
Management Data Preamble Bypass:
0 – detect SMI packets with Preamble
1 – detect SMI packets without preamble
RW
0
17.9
FARLOOPBACK
Force the module to the FAR Loop Back mode, i.e. all
the received packets are sent back simultaneously (in
100Base-TX only). This bit is only active in RMII
mode. In this mode the user needs to supply a 50MHz
clock to the PHY. This mode works even if MII Isolate
(0.10) is set.
RW
0
17.8:7
Reserved
Write as 0, ignore on read.
RW
00



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