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LAN8187 Datasheet(PDF) 46 Page - SMSC Corporation

Part # LAN8187
Description  짹15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWRTM
PDF  72 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

LAN8187 Datasheet(HTML) 46 Page - SMSC Corporation

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±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWRTM
Datasheet
Revision 1.0 (12-14-06)
46
SMSC LAN8187/LAN8187I
DATASHEET
17.6
ALTINT
Alternat Interrupt Mode.
0 = Primary interrupt system enabled (Default).
1 = Alternate interrupt system enabled.
See Section 5.3, "Interrupt Management," on page 49.
RW
0
17.5:4
Reserved
Write as 0, ignore on read.
RW
00
17.3
PHYADBP
1 = PHY disregards PHY address in SMI access
write.
RW
0
17.2
Force
Good Link Status
0 = normal operation;
1 = force 100TX- link active;
Note:
This bit should be set only during lab testing
RW
0
17.1
ENERGYON
ENERGYON – indicates whether energy is detected
on the line (see Section 5.4.5.2, "Energy Detect
Power-Down," on page 51); it goes to “0” if no valid
energy is detected within 256ms. Reset to “1” by
hardware reset, unaffected by SW reset.
RO
1
17.0
Reserved
Write as 0, ignore on read.
RW
0
Table 5.39 Register 18 - Special Modes
ADDRESS
NAME
DESCRIPTION
MODE
DEFAULT
18.15:14
MIIMODE
MII Mode: set the mode of the MII:
0 – MII interface.
1 – RMII interface
RW,
NASR
18.13:8
Reserved
Write as 0, ignore on read.
RW,
NASR
000000
18.7:5
MODE
PHY Mode of operation. Refer to Section 5.4.9.2,
"Mode Bus – MODE[2:0]," on page 53 for more
details.
RW,
NASR
XXX
EVB8700
default
111
18.4:0
PHYAD
PHY Address.
The PHY Address is used for the SMI address and for
the initialization of the Cipher (Scrambler) key. Refer
to Section 5.4.9.1, "Physical Address Bus -
PHYAD[4:0]," on page 53 for more details.
RW,
NASR
PHYAD
EVB8700
default
11111
Table 5.40 Register 27 - Special Control/Status Indications
ADDRESS
NAME
DESCRIPTION
MODE
DEFAULT
27.15
AMDIXIOCTRL
Enables the external AMDIX and CH_SELECT pins
0 - External pins AMDIX_EN and CH_SELECT control
the AMDIX.
1 - Internal bits 27.14 and 27.13 control the AMDIX.
Note:
Please see Table 4.3, “Auto-MDIX Control,”
on page 30
RW
0
Table 5.38 Register 17 - Mode Control/Status (continued)
ADDRESS
NAME
DESCRIPTION
MODE
DEFAULT



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