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CDCL1810 Datasheet(PDF) 4 Page - Texas Instruments |
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CDCL1810 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 25 page  www.ti.com DC ELECTRICAL CHARACTERISTICS AC ELECTRICAL CHARACTERISTICS CDCL1810 SLLS781A – FEBRUARY 2007 – REVISED MARCH 2007 Over recommended operating conditions (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT All outputs enabled; VDD = VDD,typ IVDD Total current from digital 1.8V supply 212 mA 650MHz LVDS input All outputs enabled; AVDD = VDD,typ IAVDD Total current from analog 1.8V supply 16 mA 650MHz LVDS input VIL,CMOS Low level CMOS input voltage VDD = 1.8V –0.2 0.6 V VIH,CMOS High level CMOS input voltage VDD = 1.8V VDD –0.6 VDD V IIL,CMOS Low level CMOS input current VDD = VDD,max, VIL = 0.0V –120 µA IIH,CMOS High level CMOS input current VDD = VDD,max, VIH = 1.9V 65 µA Low level CMOS output voltage for the VOL,SDA Sink current = 3 mA 0 0.2VDD V SDA pin IOL,CMOS Low level CMOS output current 8 mA Over recommended operating conditions (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Differential input impedance for ZD,IN 90 132 Ω the LVDS input terminals VCM,IN Common-mode voltage, LVDS 1125 1200 1375 mV input Single-ended LVDS input voltage VS,IN 100 600 mVPP swing VD,IN Differential LVDS input voltage 200 1200 mVPP swing tR,OUT, Output signal rise/fall time 20%–80% 100 ps tF,OUT VCM,OUT Common-mode voltage, CML VDD – 0.31 VDD – 0.23 VDD – 0.19 V outputs VS,OUT Single-ended CML output voltage ac-coupled 180 230 280 mVPP swing VD,OUT Differential CML output voltage ac-coupled 360 460 560 mVPP swing FIN Clock input frequency 650 MHz FOUT Clock output frequency 650 MHz 4 Submit Documentation Feedback |
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