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TMS320C6421 Datasheet(PDF) 202 Page - Texas Instruments |
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TMS320C6421 Datasheet(HTML) 202 Page - Texas Instruments |
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202 / 227 page  www.ti.com 6.15.3 EMAC Electrical Data/Timing (MII and RMII) MRCLK 2 3 1 MTCLK 2 3 1 TMS320C6421 Fixed-Point Digital Signal Processor SPRS346B – JANUARY 2007 – REVISED APRIL 2007 6.15.3.1 EMAC MII Electrical Data/Timing Table 6-57. Timing Requirements for MRCLK - MII Operation (see Figure 6-36) -400 -500 -600 NO. UNIT 10 Mbps 100 Mbps MIN MAX MIN MAX 1 tc(MRCLK) Cycle time, MRCLK(1) 400 40 ns 2 tw(MRCLKH) Pulse duration, MRCLK high 140 14 ns 3 tw(MRCLKL) Pulse duration, MRCLK low 140 14 ns (1) There is a clock ratio requirement between the system infrastructure clock, SYSCLK3, and the EMAC receive/transmit input clocks, MRCLK and MTCLK. For proper device operation, the SYSCLK3 frequency must be faster than 12.5 MHz. Figure 6-36. MRCLK Timing (EMAC - Receive) [MII Operation] Table 6-58. Timing Requirements for MTCLK - MII Operation (see Figure 6-36) -400 -500 -600 NO. UNIT 10 Mbps 100 Mbps MIN MAX MIN MAX 1 tc(MTCLK) Cycle time, MTCLK(1) 400 40 ns 2 tw(MTCLKH) Pulse duration, MTCLK high 140 14 ns 3 tw(MTCLKL) Pulse duration, MTCLK low 140 14 ns (1) There is a clock ratio requirement between the system infrastructure clock, SYSCLK3, and the EMAC receive/transmit input clocks, MRCLK and MTCLK. For proper device operation, the SYSCLK3 frequency must be faster than 12.5 MHz. Figure 6-37. MTCLK Timing (EMAC - Transmit) [MII Operation] Table 6-59. Timing Requirements for EMAC MII Receive 10/100 Mbit/s (1) (see Figure 6-38) -400 -500 NO. UNIT -600 MIN MAX 1 tsu(MRXD-MRCLKH) Setup time, receive selected signals valid before MRCLK high 8 ns (1) Receive selected signals include: MRXD3-MRXD0, MRXDV, and MRXER. Peripheral Information and Electrical Specifications 202 Submit Documentation Feedback |
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