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MRCLK (Input)

MRXD3−MRXD0,

MRXDV, MRXER (Inputs)

MTCLK (Input)

MTXD3−MTXD0,

MTXEN (Outputs)

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

Table 6-59. Timing Requirements for EMAC MII Receive 10/100 Mbit/s (see Figure 6-38) (continued)

-400

-500

NO.

UNIT

-600

MIN

MAX

th(MRCLKH-MRXD)

Hold time, receive selected signals valid after MRCLK high

Figure 6-38. EMAC Receive Interface Timing [MII Operation]

Table 6-60. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit

10/100 Mbit/s

(1) (see Figure 6-39)

-400

-500

NO.

UNIT

-600

MIN

MAX

td(MTCLKH-MTXD)

Delay time, MTCLK high to transmit selected signals valid

(1)

Transmit selected signals include: MTXD3-MTXD0, and MTXEN.

Figure 6-39. EMAC Transmit Interface Timing [MII Operation]

6.15.3.2 EMAC RMII Electrical Data/Timing

The RMREFCLK pin is used to source a clock to the EMAC when it is configured for RMII operation. The

RMREFCLK frequency should be 50 MHz

±50 PPM with a duty cycle between 35% and 65%, inclusive.

Table 6-61. Timing Requirements for RMREFCLK - RMII Operation (see Figure 6-40)

-400

-500

NO.

PARAMETER

UNIT

-600

MIN

MAX

tc(RMREFCLK)

Cycle time, RMREFCLK(1)

TBD

tw(RMREFCLKH)

Pulse duration, RMREFCLK high

tw(RMREFCLKL)

Pulse duration, RMREFCLK low

tt(RMREFCLK)

Transition time, RMREFCLK

TBD

(1)

There is a clock ratio requirement between the system infrastructure clock, SYSCLK3, and the EMAC RMII reference clock,

RMREFCLK. For proper device operation, the SYSCLK3 frequency must be faster than 12.5 MHz.

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