TMS320C6421 datasheet(204/227 Pages) TI

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RMREFCLK

(Input)

RMREFCLK

RMRXD1−RMRXD0,

RMCRSDV, RMRXER (Inputs)

RMREFCLK

RMTXD1−RMTXD0,

RMTXEN (Outputs)

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

Figure 6-40. RMREFCLK Timing [RMII Operation]

Table 6-62. Timing Requirements for EMAC RMII Receive 10/100 Mbit/s

(1) (see Figure 6-41)

-400

-500

NO.

UNIT

-600

MIN

MAX

tsu(RMRXD-REFCLKH)

Setup time, receive selected signals valid before RMREFCLK high

TBD

th(REFCLKH-RMRXD)

Hold time, receive selected signals valid after RMREFCLK high

TBD

(1)

Receive selected signals include: RMRXD1-RMRXD0, RMCRSDV, and RMRXER.

Figure 6-41. EMAC Receive Interface Timing [RMII Operation]

Table 6-63. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit

10/100 Mbit/s

(1) (see Figure 6-42)

-400

-500

NO.

UNIT

-600

MIN

MAX

td(REFCLKH-MTXD)

Delay time, RMREFCLK high to transmit selected signals valid

TBD

(1)

Transmit selected signals include: RMTXD1-RMTXD0, and RMTXEN.

Figure 6-42. EMAC Transmit Interface Timing [RMII Operation]

204

Peripheral Information and Electrical Specifications

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TMS320C6421 Datasheet(PDF) 204 Page - Texas Instruments

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