PCD5002 datasheet(25/48 Pages) PHILIPS

25 / 48 page

1997 Jun 24

Philips Semiconductors

Product speciﬁcation

Advanced POCSAG and APOC-1 Paging

Decoder

PCD5002

Fig.10 POCSAG alert timing.

handbook, full pagewidth

FC = 00

FC = 01

FC = 10

FC = 11

tALC

tALP

tALC

tALP

MLC252

8.41

Cancelling alerts

Standard POCSAG alerts (manual or automatic) are

cancelled by resetting bit D0 in the alert set-up register.

User defined alerts are cancelled by writing a zero to the

alert cadence register. Any ongoing alert is cancelled

when a reset pulse is applied to input RST.

8.42

Automatic POCSAG alerts

Standard alert patterns have been deﬁned for each

POCSAG call type, as indicated by the function bits in the

address codeword (see Table 1). The timing of these alert

patterns is shown in Fig.10. After completion of the full 16 s

alert period an interrupt is generated by status bit D4.

When enabled by SPF programming (SPF byte 03, bit D2)

standard POCSAG alerts will be automatically generated

at outputs ATL, ATH, LED and VIB upon call reception.

The alert pattern matches the call type as indicated by the

function bits in the received address codeword.

The original settings of the alert set-up register will be lost.

Bit D0 is reset after completion of the alert.

8.43

SRAM access

The on-chip SRAM can hold up to 96 bytes of call data.

Each call consists of a call header (3 bytes), message data

blocks (3 bytes per codeword) and a call terminator

(3 bytes).

The RAM is filled by the decoder and can be read via the

I2C-bus interface. The RAM is accessed indirectly by a

read address pointer and a data output register. A write

address pointer indicates the position of the last message

byte stored.

Status register bit D2 is set when the read and write

pointers are different. It is reset only when the SRAM

pointers become equal during reading, i.e. when the RAM

becomes empty.

Status bit D3 is set when the read and write pointers

become equal. This can be due to a RAM empty or a RAM

full condition. It is reset after a status read operation.

Interrupts are generated as follows:

• When status bit D2 is set and the receiver is disabled

(RXE = 0); data is available for reading

• Immediately when status bit D3 is set: RAM is either

empty (status bit D2 = 0) or full (status bit D2 = 1).

To avoid loss of data due to RAM overflow at least 3 bytes

of data must be read during reception of the codeword

following the ‘RAM full’ interrupt.

PCD5002 Datasheet(PDF) 25 Page - NXP Semiconductors

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