PCD5002 datasheet(28/48 Pages) PHILIPS

28 / 48 page

1997 Jun 24

Philips Semiconductors

Product speciﬁcation

Advanced POCSAG and APOC-1 Paging

Decoder

PCD5002

Table 23 Special programmed functions (EEPROM address 00H)

Table 24 Special programmed functions (EEPROM address 01H)

Note

1. Since the exact establishment time is related to the programmed bit rate, Table 25 shows the values for the various

bit rates.

BIT (MSB: D7)

VALUE

DESCRIPTION

POCSAG decoding enabled

APOC-1 decoding enabled

cycle length: 5 batches

cycle length: 15 batches

D5 to D2 (MSB: D5)

0 to 4

batch number (D1 = 0, MSB is ignored)

0 to 14

batch number (D1 = 1)

continuous data decoding enabled

received data inversion enabled

BIT (MSB: D7)

VALUE

DESCRIPTION

D1 and D0

0 0

5 ms receiver establishment time (nominal); note 1

0 1

10 ms

1 0

15 ms

1 1

30 ms

D3 and D2

0 0

20 ms oscillator establishment time (nominal); note 1

0 1

30 ms

1 0

40 ms

1 1

50 ms

D5 and D4

0 0

512 bits/s received bit rate

0 1

1024 bits/s (not used in POCSAG)

1 0

1200 bits/s

1 1

2400 bits/s

synthesizer interface enabled (programming at switch-on)

voltage converter enabled

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