PCD5002 datasheet(27/48 Pages) PHILIPS

27 / 48 page

1997 Jun 24

Philips Semiconductors

Product speciﬁcation

Advanced POCSAG and APOC-1 Paging

Decoder

PCD5002

After writing each block a pause of 7.5 ms (max.) is

required to complete the internal programming operation.

During this time the external microcontroller may generate

an I2C-bus STOP condition. If another I2C-bus transfer is

initiated the decoder will pull SCL LOW during this pause.

After writing the EEPROM programming enable bit (D1) in,

the control register must be reset.

8.53

Invalid write address

When an invalid write address is used, the column counter

bits (D2 to D0) are forced to zero before being loaded into

the address pointer. The row counter bits are used

normally.

8.54

Incomplete programming sequence

A programming sequence may be aborted by an I2C-bus

STOP condition. The EEPROM programming enable

bit (D1) in the control register must then be reset.

Any bytes received from the last 6-byte block will be

ignored and the contents of this (incomplete) EEPROM

block will remain unchanged.

8.55

Unused EEPROM locations

A total of 20 EEPROM bytes are available for general

purpose storage (see Table 22).

Table 22 Unused EEPROM addresses

Note

1. When using bytes 04H and 05H, care must be taken to

preserve the SPF information stored in

bytes 00H to 03H.

8.56

Special programmed function allocation

The SPF bit allocation in the EEPROM is shown in

Tables 23 to 27. The SPF bits are located in row 0 of the

EEPROM and occupy 4 bytes.

Bytes 04H and 05H are not used and are available for

general purpose storage.

ROW

HEX

04 and 05(1)

528 to 2D

630 to 35

738 to 3D

Fig.11 EEPROM organization and access.

handbook, full pagewidth

COLUMN

ROW

ADDRESS

POINTER

ROW COLUMN

I/O REGISTER

SPF bits

Synthesizer data

Identifiers

unused bytes

MLC254

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