PCD5096 datasheet(23/52 Pages) PHILIPS

23 / 52 page

1997 Jan 22

Philips Semiconductors

Preliminary speciﬁcation

Universal codec

PCD5096

Table 28 Timing parameters in IOM mode; see Fig.7

Notes

1. Corresponds to the highest DCL frequency allowed (4.096 MHz) with a 10% margin.

2. CL = 150 pF.

Table 29 Timing parameters in Speech mode; see Fig.8

Notes

1. Corresponds to the DCL frequency (2.048 MHz) with a 10% margin.

2. CL = 150 pF.

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

tr(DCL)

data clock rise time

−

tf(DCL)

data clock fall time

−

TDCL

data clock period

220(1)

−

tWH(DCL)

data clock pulse width HIGH

−

tWL(DCL)

data clock pulse width LOW

−

tr(FSC)

frame sync rise time

−

tf(FSC)

frame sync fall time

−

td(DCL-FSC)

frame delay DCL to FSC

−tWL(DCL)

tsu(FSC-DCL)

frame set-up time FSC to DCL

−

tWH(FSC)

frame width HIGH

130

−

td(DLC-DO)

data delay from data clock

−

100(2)

td(FSC-DO)

data delay from frame

−

150(2)

tsu(DI-DCL)

set-up time DI to DCL

tWH(DCL)

−

th(DI)

data hold time

−

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

td(DCL-FSC)

frame delay time DCL to FSC

−twL(DCL)

100

tsu(FSC-DCL)

frame set-up time FSC to DCL

−

tWH(FSC)

frame width HIGH

130

−

TDCL

data clock period

440(1)

−

tWL(DCL)

data clock pulse width LOW

150

−

tWH(DCL)

data clock pulse width HIGH

150

−

td(DCL-DO)

data delay from clock

−

100(2)

tsu(DI-DCL))

set-up time DI to DCL

−

th(DI)

data hold time

−

PCD5096 Datasheet(PDF) 23 Page - NXP Semiconductors

PCD5096 Datasheet(HTML) 23 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL