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PCF8584 Datasheet(PDF) 24 Page - NXP Semiconductors |
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PCF8584 Datasheet(HTML) 24 Page - NXP Semiconductors |
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24 / 40 page  1997 Oct 21 24 Philips Semiconductors Product specification I2C-bus controller PCF8584 12 I2C-BUS TIMING SPECIFICATIONS All the timing limits are valid within the operating supply voltage and ambient temperature range; VDD =5V ±10%; Tamb = −40 to +85 °C; and refer to VIL and VIH with an input voltage of VSS to VDD. 13 PARALLEL INTERFACE TIMING All the timing limits are valid within the operating supply voltage and ambient temperature range: VDD =5V ±10%; Tamb = −40 to +85 °C; and refer to VIL and VIH with an input voltage of VSS to VDD. CL = 100 pF; RL = 1.5 kΩ (connected to VDD) for open-drain and high-impedance outputs, where applicable (for measurement purposes only). SYMBOL PARAMETER MIN. TYP. MAX. UNIT fSCL SCL clock frequency −− 100 kHz tSW tolerable spike width on bus −− 100 ns tBUF bus free time 4.7 −− µs tSU;STA START condition set-up time 4.7 −− µs tHD;STA START condition hold time 4.0 −− µs tLOW SCL LOW time 4.7 −− µs tHIGH SCL HIGH time 4.0 −− µs tr SCL and SDA rise time −− 1.0 µs tf SCL and SDA fall time −− 0.3 µs tSU;DAT data set-up time 250 −− ns tHD;DAT data hold time 0 −− ns tVD;DAT SCL LOW to data out valid −− 3.4 µs tSU;STO STOP condition set-up time 4.0 −− µs SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT tr clock rise time see Fig.14 −− 6ns tf clock fall time see Fig.14 −− 6ns tCLK input clock period (50% ±5% duty factor) see Fig.14 83 − 333 ns tCLRL CS set-up to RD LOW see Fig.16 and note 1 20 −− ns tCLWL CS set-up to WR LOW see Fig.15 and note 1 20 −− ns tRHCH CS hold from RD HIGH see Fig.16 0 −− ns tWHCH CS hold from WR HIGH see Fig.15 0 −− ns tAVWL A0 set-up to WR LOW see Fig.15 10 −− ns tAVRL A0 set-up to RD LOW see Fig.16 10 −− ns tWHAI A0 hold from WR HIGH see Fig.15 20 −− ns tRHAI A0 hold from RD HIGH see Fig.16 10 −− ns tWLWH WR pulse width see Fig.15 230 − 1000 ns tRLRH RD pulse width see Fig.16 230 − 1000 ns tDVWH data set-up before WR HIGH see Fig.15 150 −− ns tRLDV data valid after RD LOW see Fig.16 − 160 180 ns tWHDI data hold after WR HIGH see Fig.15 20 −− ns tRHDF data bus floating after RD HIGH see Fig.16 −− 150 ns |
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