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PCF8584 Datasheet(PDF) 25 Page - NXP Semiconductors |
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PCF8584 Datasheet(HTML) 25 Page - NXP Semiconductors |
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25 / 40 page  1997 Oct 21 25 Philips Semiconductors Product specification I2C-bus controller PCF8584 Notes 1. A minimum of 6 clock cycles must elapse between consecutive parallel-bus accesses when the I2C-bus controller operates at 8 or 12 MHz. This may be reduced to 3 clock cycles for lower operating frequencies. 2. Not for S1. tAVCL A0 set-up to CS LOW see Figs 17 and 18 10 −− ns tWLCL R/WR set-up to CS LOW see Fig.17 10 −− ns tRHCL R/WR set-up to CS LOW see Fig.18 10 −− ns tCLDV data valid after CS LOW see Fig.18 and note 2 − 160 180 ns tCLDL DTACK LOW after CS LOW see Figs 17 and 18 − 2tCLK +75 3tCLK + 150 ns tCHAI A0 hold from CS HIGH see Fig.18 0 −− ns tCHRL R/WR hold from CS HIGH see Fig.18 0 −− ns tCHWH R/WR hold from CS HIGH see Fig.17 0 −− ns tCHDF data bus float after CS HIGH see Fig.18 −− 150 ns tCHDE DTACK HIGH from CS HIGH see Figs 17 and 18 − 100 120 ns tCHDI data hold after CS HIGH see Fig.17 0 −− ns tDVCL data set-up to CS LOW see Fig.17 0 −− ns tALIE INT HIGH from IACK LOW see Figs 19 and 20 − 130 180 ns tALDV data valid after IACK LOW see Figs 19 and 20 − 200 250 ns tALAE IACK pulse width see Fig.20 230 −− ns tAHDI data hold after IACK HIGH see Fig.20 −− 30 ns tALDL DTACK LOW from IACK LOW see Fig.20 − 2tCLK +75 3tCLK + 150 ns tAHDE DTACK HIGH from IACK HIGH see Fig.20 − 120 140 ns tW4 RESET pulse width see Fig.21 30tCLK −− ns tW5 STROBE pulse width see Fig.22 8tCLK 8tCLK +90 − ns tCLCL CS LOW see Figs 17 and 18 − tCLDL +tCHDE − ns SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
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