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PCF8801 Datasheet(PDF) 4 Page - NXP Semiconductors |
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PCF8801 Datasheet(HTML) 4 Page - NXP Semiconductors |
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4 / 20 page ![]() 2000 Feb 04 4 Philips Semiconductors Product specification LCD driver for 140 × 2 segments PCF8801 PINNING Note 1. These symbols simplify descriptions in this data sheet where several pads have the same function and also indicate the direction of data on pads which can be selected to be either an input or an output. SYMBOL PAD SIMPLIFIED SYMBOL(1) DESCRIPTION VDD1 to VDD4 28, 27, 3, 4 VDD Power supply for output drivers, backplane drivers and LCD bias generator; 4 pads connected internally VSS1 to VSS4 30, 29, 1, 2 VSS Ground for output drivers, backplane drivers and LCD bias generator; 4 pads connected internally VDD5 16 VDD Power supply for remaining circuitry; connect externally to VDD1 to VDD4 VSS5 15 VSS Ground for remaining circuitry; connect externally to VSS1 to VSS4 REXT 10 Enable internal oscillator input; connected via an external resistor RESET 14 Reset input; active HIGH T1 to T3 13, 17, 18 Test pads; must remain unconnected COM1_1, COM1_2 31, 173 COM1 First pair of identical 3-level LCD backplane outputs; each pad is located on opposite sides of the die COM2_1, COM2_2 32, 174 COM2 Second pair of identical 3-level LCD backplane outputs; each pad is located on opposite sides of the die DIR 19 Data direction control input; its voltage level determines the direction in which data is shifted S1 to S140 33 to 172 LCD driver outputs DI1, DI2 24, 7 DI Data input; the status of DIR determines which pad is valid; each pad is located on opposite sides of the die DO1, DO2 23, 8 DO Data outputs; both identical; both always valid; for cascade use; each pad is located on opposite sides of the die LDP1, LDP2 26, 5 LDPI, LDPO Data load control input (LDPI) and output (LDPO) on rising edge; the status of DIR determines which pad is valid; each pad is located on opposite sides of the die LDN1, LDN2 25, 6 LDNI, LDNO Data load control input (LDNI) and output (LDNO) on falling edge; the status of DIR determines which pad is valid; each pad is located on opposite sides of the die CLK1, CLK2 22, 9 CLKI, CLKO Data shift clock input (CLKI) and output (CLKO); the status of DIR determines which pad is valid; for cascade use; each pad is located on opposite sides of the die OSC1, OSC2 21, 11 OSCI, OSCO LCD multiplexing clock input (OSCI) and output (OSCO); the status of DIR determines which pad is valid; each pad is located on opposite sides of the die INT_OSCO1, INT_OSCO2 20, 12 INT_OSCO Internal oscillator outputs; both identical; each pad is located on opposite sides of the die |
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