AWR1642 datasheet(39/75 Pages) TI1

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Table 7-23. SPI Switching Characteristics Peripheral Mode

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

SS6

td(SPICLK-SOMI)

Delay time, SPI_CLK active edge to McSPI_somi transition

5.77

SS7

tsk(CS-SOMI)

Delay time, SPI_CS[x] active edge to McSPI_somi transition

5.77

(1)

P = This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and

capture input data.

(2)

P = SPICLK period.

(3)

PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.

7.13.4.4.2 Timing and Switching Characteristics for SPI Output Timings—Secondary Mode

SPI_CS[x]

(IN)

SPI_SCLK

(IN)

SPI_SCLK

(IN)

SPI_D[x]

(IN)

SPI_CS[x]

(IN)

SPI_SCLK

(IN)

SPI_SCLK

(IN)

SPI_D[x]

(IN)

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit 0

PHA=0

EPOL=1

POL=0

POL=1

POL=0

POL=1

PHA=1

EPOL=1

SS3

SS1

SS3

SS1

SS3

SS1

SS2

SS1

SS8

SS9

SS8

SS9

SS2

SS3

SS2

SS4

SS5

SS4

SS5

SS4

SS5

SPRSP08_TIMING_McSPI_04

Figure 7-13. SPI Timing - Peripheral mode Receive

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AWRL6432

SWRS295A – DECEMBER 2022 – REVISED MARCH 2024

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