AWR1642 datasheet(49/75 Pages) TI1

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7.13.11.3 QSPI Switching Characteristics

NO.

PARAMETER

MIN

TYP

MAX

UNIT

tc(SCLK)

Cycle time, sclk

12.5

tw(SCLKL)

Pulse duration, sclk low

Y*P – 3(1) (2)

tw(SCLKH)

Pulse duration, sclk high

Y*P – 3(1) (2)

td(CS-SCLK)

Delay time, sclk falling edge to cs active edge

–M*P – 1(2) (3)

–M*P + 2.5(2)

(3)

td(SCLK-CS)

Delay time, sclk falling edge to cs inactive edge

N*P – 1(2) (3)

N*P + 2.5(2)

(3)

td(SCLK-D1)

Delay time, sclk falling edge to d[1] transition

–2

tena(CS-D1LZ)

Enable time, cs active edge to d[1] driven (lo-z)

–P – 4(2)

–P +1(2)

tdis(CS-D1Z)

Disable time, cs active edge to d[1] tri-stated (hi-z)

–P – 4(2)

–P +1(2)

td(SCLK-D1)

Delay time, sclk first falling edge to first d[1] transition

(for PHA = 0 only)

–2 – P(2)

4– P(2)

Q12

tsu(D-SCLK)

Setup time, d[3:0] valid before falling sclk edge

Q13

th(SCLK-D)

Hold time, d[3:0] valid after falling sclk edge

Q14

tsu(D-SCLK)

Setup time, final d[3:0] bit valid before final falling

sclk edge

5 — P(2)

Q15

th(SCLK-D)

Hold time, final d[3:0] bit valid after final falling sclk

edge

1 + P(2)

(1)

The Y parameter is defined as follows: If DCLK_DIV is 0 or ODD then, Y equals 0.5. If DCLK_DIV is EVEN then, Y equals

(DCLK_DIV/2) / (DCLK_DIV+1). For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle

distortion. All required details about clock division factor DCLK_DIV can be found in the device-specific Technical Reference Manual.

(2)

P = SCLK period in ns.

(3)

M = QSPI_SPI_DC_REG.DDx + 1, N = 2

Figure 7-18. QSPI Read (Clock Mode 0)

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AWRL6432

SWRS295A – DECEMBER 2022 – REVISED MARCH 2024

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