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PC3S12XEP100J1MVLR Datasheet(PDF) 64 Page - Freescale Semiconductor, Inc |
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PC3S12XEP100J1MVLR Datasheet(HTML) 64 Page - Freescale Semiconductor, Inc |
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64 / 1036 page  Chapter 1 Device Overview MC9S12XE-Family MC9S12XE-Family Reference Manual , Rev. 1.07 64 Freescale Semiconductor 1.3 System Clock Description The clock and reset generator module (CRG) provides the internal clock signals for the core and all peripheral modules. Figure 1-8 shows the clock connections from the CRG to all modules. Consult the CRG specification for details on clock generation. Figure 1-8. Clock Connections The system clock can be supplied in several ways enabling a range of system operating frequencies to be supported: • The on-chip phase locked loop (PLL) • the PLL self clocking • the oscillator The clock generated by the PLL or oscillator provides the main system clock frequencies core clock and bus clock. As shown in Figure 1-8, these system clocks are used throughout the MCU to drive the core, the memories, and the peripherals. SCI0 . . SCI 7 SPI0 . . SPI2 IIC0 & IIC1 ATD0 & ATD1 CAN0 . . CAN4 CRG Bus Clock EXTAL XTAL Core Clock Oscillator Clock RAM S12X XGATE FLASH & PIT ECT PIM EEE PWM TIM |
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