PC3S12XEP100J1MVLR datasheet(69/1036 Pages) FREESCALE

69 / 1036 page

Chapter 1 Device Overview MC9S12XE-Family

MC9S12XE-Family Reference Manual Rev. 1.07

Freescale Semiconductor

MPU is set, access to system resources is only allowed if enabled by a memory range descriptor as deﬁned

in the Memory Protection Unit (MPU) description.

1.4.4.2

User State

This state is intended for carrying out system tasks and is entered by setting the U bit of the condition codes

state and access to system resources is only allowed in if enabled by a memory range descriptor as deﬁned

in the Memory Protection Unit (MPU) description.

1.5

Security

The MCU security feature allows the protection of the on chip Flash and emulated EEPROM memory. For

a detailed description of the security features refer to the S12X9SEC description.

1.6

Resets and Interrupts

Consult the S12XCPU manual and the S12XINT description for information on exception processing.

1.6.1

Resets

Resets are explained in detail in the Clock Reset Generator (CRG) description.

1.6.2

Vectors

Table 1-13 lists all interrupt sources and vectors in the default order of priority. The interrupt module

(S12XINT) provides an interrupt vector base register (IVBR) to relocate the vectors. Associated with each

I-bit maskable service request is a conﬁguration register. It selects if the service request is enabled, the

service request priority level and whether the service request is handled either by the S12X CPU or by the

XGATE module.

PC3S12XEP100J1MVLR Datasheet(PDF) 69 Page - Freescale Semiconductor, Inc