PC3S12XEP100J1MVLR datasheet(85/1036 Pages) FREESCALE

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Chapter 2 Port Integration Module (S12XEPIMV1)

MC9S12XE-Family Reference Manual Rev. 1.07

Freescale Semiconductor

2.2

External Signal Description

This section lists and describes the signals that do connect off-chip.

Table 2-1 shows all the pins and their functions that are controlled by the Port Integration Module. Refer

to the SOC Guide for the availability of the individual pins in the different package options.

NOTE

If there is more than one function associated with a pin, the priority is

indicated by the position in the table from top (highest priority) to bottom

(lowest priority).

Table 2-1. Pin Functions and Priorities

Port

Pin Name

Pin Function

& Priority1

I/O

Description

Pin Function

after Reset

BKGD

MODC 2

MODC input during RESET

BKGD

I/O S12X_BDM communication pin

PA[7:0]

ADDR[15:8]

mux

IVD[15:8] 3

High-order external bus address output

(multiplexed with IVIS data)

Mode

dependent 4

GPIO

I/O General-purpose I/O

PB[7:1]

ADDR[7:1]

mux

IVD[7:1] 3

Low-order external bus address output

(multiplexed with IVIS data)

Mode

dependent 4

GPIO

I/O General-purpose I/O

PB[0]

ADDR[0]

mux

IVD0 3

Low-order external bus address output

(multiplexed with IVIS data)

UDS

Upper data strobe

GPIO

I/O General-purpose I/O

PC[7:0]

DATA[15:8]

I/O High-order bidirectional data input/output

Conﬁgurable for reduced input threshold

Mode

dependent 4

GPIO

I/O General-purpose I/O

PD[7:0]

DATA[7:0]

I/O Low-order bidirectional data input/output

Conﬁgurable for reduced input threshold

Mode

dependent 4

GPIO

I/O General-purpose I/O

PC3S12XEP100J1MVLR Datasheet(PDF) 85 Page - Freescale Semiconductor, Inc

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