AD9211

Rev. 0 | Page 24 of 28

Table 11. Serial Timing Definitions

Parameter

Timing (minimum, ns)

Description

5

Setup time between the data and the rising edge of SCLK

2

Hold time between the data and the rising edge of SCLK

40

Period of the clock

5

Setup time between CSB and SCLK

2

Hold time between CSB and SCLK

16

Minimum period that SCLK should be in a logic high state

16

Minimum period that SCLK should be in a logic low state

1

Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK

falling edge (not shown in Figure 51)

5

Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK

rising edge (not shown in Figure 51)

Table 12. Output Data Format

Input (V)

Condition (V)

Offset Binary

Output Mode

D11 to D0

Twos Complement Mode

D11 to D0

Gray Code Mode

(SPI Accessible)

D11 to D0

OR

VIN+ − VIN−

< 0.62

0000 0000 00

0000 0000 00

0000 0000 00

1

VIN+ − VIN−

= 0.62

0000 0000 00

0000 0000 00

0000 0000 00

0

VIN+ − VIN−

= 0

0000 0000 00

0000 0000 00

0000 0000 00

0

VIN+ − VIN−

= 0.62

1111 1111 11

1111 1111 11

0000 0000 00

0

VIN+ − VIN−

> 0.62 + 0.5 LSB

1111 1111 11

1111 1111 11

0000 0000 00

1