Data Sheet

ADPA1116

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 6 of 17

Figure 2. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 8, 9, 16, 17, 24, 25, 32

GND

Ground. The GND pins must be connected to RF and DC ground. See Figure 5 for the interface schematic.

2 to 6, 10 to 15, 19 to 23, 27, 28, 30

NIC

No Internal Connection. The NIC pins are not connected internally. For normal operation, connect to ground.

7

RFIN

RF Input. The RFIN pin is AC-coupled and internally matched to 50 Ω. See Figure 3 for the interface schematic.

18

RFOUT

RF Output. The RFOUT pin is AC-coupled and internally matched to 50 Ω. See Figure 6 for the interface

schematic.

26

VDD2

Drain Bias Pin for the Second Stage. See Figure 6 for the interface schematic.

29

VDD1

Drain Bias Pin for the First Stage. See Figure 7 for the interface schematic.

31

VGG1

Gate Bias for Both Stages of the Amplifier. The VGG1 pin is used to set the IDQ of the amplifier. See Figure 4 for

the interface schematic.

EPAD

Exposed Pad. Connect the exposed pad to a ground plane that has low electrical and thermal impedance.

INTERFACE SCHEMATICS

Figure 3. RFIN Interface Schematic

Figure 4. VGG1 Interface Schematic

Figure 5. GND Interface Schematic

Figure 6. VDD2 and RFOUT Interface Schematic

Figure 7. VDD1 Interface Schematic