SP6126 datasheet(8/14 Pages) SIPEX

8 / 14 page

Mar 29-07 RevD

SP6126: TSOT-6 PFET Buck Controller

 2007 Sipex Corporation

A sudden decrease in IOUT forces the energy

surplus in L to be absorbed by COUT. This

causes an overshoot in output voltage that is

corrected by power switch reduced duty cycle.

Use the following equation to calculate COUT:













−

Vout

Vos

Cout

Where:

L is the output inductance

2 is the step load high current

1 is the step load low current

Vos is output voltage including overshoot

VOUT is steady state output voltage

Output voltage undershoot calculation is more

complicated. Test results for SP6126 buck

circuits show that undershoot is approximately

equal to overshoot. Therefore above equation

provides a satisfactory method for calculating

COUT.

Select ESR such that output voltage ripple

(VRIP) specification is met. There are two

components to VRIP: First component arises

from charge transferred to and from COUT

during each cycle. The second component of

VRIP is due to inductor ripple current flowing

through output capacitor’s ESR. It can be

calculated from:













Cout

ESR

Irip

Vrip

Where:

IRIP

is inductor ripple current

fs is switching frequency

COUT is output capacitor calculated above

Note that a smaller inductor results in a higher

IRIP

, therefore requiring a larger COUT and/or

lower ESR in order to meet VRIP.

Input Capacitor Selection

Select

the

input

capacitor

for

Voltage,

Capacitance, ripple current, ESR and ESL.

Voltage rating is nominally selected to be twice

the input voltage. The RMS value of input

capacitor current, assuming a low inductor

ripple current (IRIP), can be calculated from:

(

)

Iout

Icin

−

In general total input voltage ripple should be

kept below 1.5% of VIN (not to exceed 180mV).

Input voltage ripple has three components:

ESR and ESL cause a step voltage drop upon

turn on of the MOSFET. During on time

capacitor discharges linearly as it supplies

IOUT-Iin. The contribution to Input voltage ripple

by each term can be calculated from:

(

)

Vin

Cin

Vout

Vin

Vout

Iout

Cin

−

∆

(

)

Irip

Iout

ESR

−

∆

(

)

Trise

Irip

Iout

ESL

−

∆

Where Trise is the rise time of current through

capacitor

Total input voltage ripple is sum of the above:

ESL

ESR

Cin

Tot

∆

GENERAL OVERVIEW

SP6126 Datasheet(PDF) 8 Page - Sipex Corporation

SP6126 Datasheet(HTML) 8 Page - Sipex Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Datasheet Download

Link URL