KS8993ML datasheet(21/85 Pages) MICREL

21 / 85 page

Micrel, Inc.

KS8993M/ML/MI

April 2005

M9999-041205

PLL Clock Synthesizer

The KS8993M generates 125MHz, 31.25MHz, 25MHz, and 10MHz clocks for system timing. Internal clocks are

generated from an external 25MHz crystal or oscillator.

Scrambler/De-scrambler (100BASE-TX Only)

The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline

wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR).

The scrambler can generate a 2047-bit non-repetitive sequence. The receiver will then de-scramble the incoming

data stream with the same sequence at the transmitter.

100BASE-FX Operation

100BASE-FX operation is very similar to 100BASE-TX operation with the differences being that the scrambler /

de-scrambler and MLT3 encoder / decoder are bypassed on transmission and reception. In 100BASE-FX mode,

the auto negotiation feature is bypassed since there is no standard that supports fiber auto negotiation. The auto-

MDI/MDI-X feature is also disabled.

100BASE-FX Signal Detection

In fiber operation, the KS8993M’s FXSD1 (fiber signal detect) input pin is usually connected to the fiber

transceiver’s SD (signal detect) output pin. 100BASE-FX mode is activated when the FXSD1 input pin is greater

than 1V. When FXSD1 is between 1V and 1.8V, no fiber signal is detected and a far end fault (FEF) is generated.

When FXSD1 is over 2.2V, the fiber signal is detected.

Alternatively, the designer may choose not to implement the FEF feature. In this case, the FXSD1 input pin is tied

high to force 100BASE-FX mode.

100BASE-FX signal detection is summarized in the following table:

Part Number

Mode

Less than 0.2V

TX mode

Greater than 1V, but less than 1.8V

FX mode

No signal detected.

Far-end fault generated

Greater than 2.2V I

FX mode

Signal detected

Table 1. FX and TX Mode Selection

To ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceiver’s SD output

voltage swing to match the KS8993M’s FXSD1 input voltage threshold.

100BASE-FX Far End Fault

An FEF occurs when the signal detection is logically false on the receive side of the fiber transceiver. The

KS8993M detects a FEF when its FXSD1 input is between 1.0V and 1.8V. When an FEF occurs, the transmission

side signals the other end of the link by sending 84 1’s followed by a zero in the idle period between frames.

Upon receiving an FEF, the LINK will go down (even when a fiber signal is detected) to indicate a fault condition.

The transmitting side is not affected when an FEF is received, and will continue to send out its normal transmit

pattern from the MAC. By default, FEF is enabled. The FEF feature can be disabled through register setting.

10BASE-T Transmit

The output 10BASE-T driver is incorporated into the 100BASE-T driver to allow transmission with the same

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