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33385 Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc

Part # 33385
Description  Quad Low-side Driver
PDF  18 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

33385 Datasheet(HTML) 7 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
Freescale Semiconductor
7
33385
ELECTRICAL CHARACTERISTICS
DYNAMIC CHARACTERISTIC
DYNAMIC CHARACTERISTIC
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 7.0 V
≤ V
SUP ≤ 18 V, - 40°C ≤ T
A ≤ 125°C, GND = 0 V unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
INPUTS
Input Frequency (NON1 to NON4)
fIN
0.0
1000
Hz
OUTPUTS TIMING
Positive Output Voltage Ramp (with inductive load)
VOUT = 4V... 16V
VOUT = 16V... Vclp
OVRP1
OVRP2
2.0
3.5
3.0
6.0
5.0
10
V/
µs
V/
µs
Negative Output Voltage Ramp
(25%... 75%)
OVRN
1.75
3.0
4.0
V/
µs
Internal Switch-on-Time Charge Pump
(NON = LOW... VGATE = 0.9 * VBAT)
tDCP
40
µs
Turn ON Delay
(NON = 50%, VOUT = 0.9 * VBAT)
tDON
1.0
2.5
5.0
µs
Turn OFF Delay
(NON = 50%, VOUT = 0.1 * VBAT)
(NON = 50%, VOUT = 4V)
tDOFFA
tDOFFB
1.0
4.7
3.0
7.5
µs
µs
Undervoltage Protection
Max ON time after a output voltage ramp from
0V to 25V at VCC = 0V...VCCPRO
tRPON
100
µs
Matching Turn ON Delay
(NON = 50%, VOUT = 0.9 * VBAT)
tMON
- 3.0
3.0
µs
Rise time Turn OFF
(10% - 90% of VCLP)
tROFF
8.5
12
µs
DIAGNOSTIC
Short to GND Filter Time
TSCG
140
250
µs
Open Load Filter Time
tOL
140
250
µs
SERIAL DIAGNOSTIC LINK : LOAD CAPACITOR AT SDI AND SDO = 100PF
Clock Frequency (50% duty cycle)
fCLK
3.0
MHz
Minimum Time CLK = HIGH
tCLH
100
ns
Minimum Time CLK = LOW
tCLL
100
ns
Propagation Delay (CLF Data at SDO valid)
tPCLD
100
ns
NCS = LOW to Data at SDO Valid
tPCLD
100
ns
CLK Low Before NCS Low
(Setup time CLK to NCS change High/Low)
tSCLCH
100
ns
CLK Change Low/High after NCS = Low
tHCLCL
100
ns
SDI Input Set up Time
(CLK change High/Low after SDI data valid)
tSCLD
20
ns
SDI Input Hold Time (SDI data hold after CLK change High/Low)
tHCLD
20
ns
CLK Low Before NCS High
tSCLCL
150
ns



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