OXCF950 datasheet(15/66 Pages) OXFORD

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OXCF950 rev B DATA SHEET

OXFORD SEMICONDUCTOR, INC.

Local Bus Address1 (hex)

CF/PCMCIA offset from

address 0 for Local Bus

function in IO space (hex)

Table 5: Local Bus mapping in I/O space

Note 1: Although only 4 bits of IO address space are

requested by the default CIS in the device, the address

range may be extended past these four bits. This can be

achieved by modifying the CIS, via the EEPROM, and

connecting the extended address bits to the external local

bus device. A3 is used by the OXCF950 to determine

internal/external accesses, so a linear address range for

external devices over 8 addresses is not possible.

5.3.3

Accessing Local Configuration Registers

The local configuration registers are a set of device specific registers, which can be accessed via standard IO mapping. As the

device is configured as a single function device, no base address is required to access the local configuration registers. Since IO

mapping is used, access to the local configuration registers is permitted only after the card has been configured. Once the

Configuration Options Register has been set in the Attribute area, the local configuration registers can be accessed following the

mapping shown in Table 6. This access is always permitted in Normal Mode. In Local Bus Mode access is only permitted if bit[0]

is set to ‘1’ in the MDR register in the UART, otherwise the local bus will be accessed rather than the local configuration

registers. In Generic Normal mode, the MDR register causes the configuration registers to overlay the UART address space (0 to

7).

Since the local configuration registers can be accessed in a variety of ways, it can complicate driver writing tasks.

The following sequence can be used to ensure correct access in Generic, Normal or Local Bus Modes.

1. Write to UART SPR register (offset 7) with 0xFE. This sets the ICR to point to the MDR register.

2. Write to UART ICR register (offset 5) with 0x01. This sets bit 0 of the MDR register. The configuration registers are

now accessible, but they may be in address range 0 to 7 or 8 to 15 depending on Generic mode or not.

3. Read offset 7. If bit 7 is set, the configuration registers can be found in the offset address range 8 to 15. If bit 7 is clear,

the registers are overlaying the UART registers and can be found in the offset address range 0 to 7.

4. Using the offset discovered in (3) access the required local configuration registers.

5. Write to offset 7 with 0xfe, followed by a write to offset 5 with 0. This will switch back to normal operation.

CF/PCMCIA offset from address 0 for local

configuration registers in IO space (hex)

8 (0 in Generic mode)

EEPROM Status and Control register

9 (1 in Generic mode)

Multi-Purpose I/O Configuration register

A (2 in Generic mode)

UART Divider/Interrupt Pulse Width Divider register

B (3 in Generic mode)

Mode Status register

C (4 in Generic mode)

Interrupt Status register

D (5 in Generic mode)

Soft UART/Local Bus reset register

E (6 in Generic mode)

Generic Mode control

F (7 in Generic mode)

Page switch out control (in Generic Mode)

Table 6: Local Configuration Register's mapping in I/O space

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