6.3 Feature Description

6.3.1 Undervoltage Lockout

The TPSM81033 has a built-in undervoltage lockout (UVLO) circuit to ensure the device working properly. When

the analog input voltage (AVIN) is above the UVLO rising threshold of 1.7V (typical), the TPSM81033 can be

enabled to boost the output voltage. The device is disabled when the falling voltage at the AVIN pin trips the

UVLO falling threshold, which is 1.6V (typical). A hysteresis of 100mV (typical) is added so that the device

cannot be enabled again until the input voltage exceeds 1.7V (typical). This function is implemented to prevent

the device from malfunctioning when the input voltage is between UVLO rising and falling threshold.

6.3.2 Enable and Soft Start

When the input voltage is above the UVLO rising threshold and the EN pin is pulled to a voltage above 1.2V,

the TPSM81033 is enabled and starts up. To minimize the inrush current during start up, the TPSM81033 has

a soft start up function. At the beginning, the TPSM81033 enters pre-charge phase and charges the output

capacitors with a current of approximately 330mA when the output voltage is below 0.4V. When the output

voltage is charged above 0.4V, the output current is changed to having output current capability to drive the 2Ω

resistance load. To minimize the inrush current further, the TPSM810333 has a maximum pre-charge current

of 900mA(typical). After the output voltage reaches the input voltage, the TPSM81033 starts switching, and the

reference voltage ramps up a 0.8mV/μs. When the voltage at the EN pin is below 0.4V, the internal enable

comparator turns the device into shutdown mode. In the shutdown mode, the device is entirely turned off. The

output is disconnected from input power supply.

6.3.3 Setting the Output Voltage

There are two ways to set the output voltage of the TPSM81033: adjustable or fixed. If the FB is connected to

VIN, the TPSM81033 works as a fixed 5.0V output voltage version, the TPSM81033 uses the internal resistor

divider.

The output voltage is also can be set by an external resistor divider (R1, R2 in Figure 7-1). When the output

voltage is regulated, the typical voltage at the FB pin is VREF. Thus the resistor divider is determined by Equation

2.

OUT

REF

V

R1

1

R2

V

§

·

u

¨

¸

©

¹

(1)

where

• VOUT is the regulated output voltage

• VREF is the internal reference voltage at the FB pin

6.3.4 Pass-Through Operation

When the input voltage is higher than the setting output voltage, the output voltage is higher than the target

regulation voltage, the device works in pass-through mode. When the output voltage is 101% of the setting

target voltage, the TPSM81033 stops switching and fully turns on the high-side PMOS FET. The output voltage

is the input voltage minus the voltage drop across the DCR of the inductor and the RDS(on) of the PMOS FET.

When the output voltage drops below the 97% of the setting target voltage as the input voltage declines or the

load current increases, the TPSM81033 resumes switching again to regulate the output voltage.

6.3.5 Power Good Indicator

The TPSM81033 integrates a power good indicator to simplify sequencing and supervision. The power-good

output consists of an open-drain NMOS, requiring an external pullup resistor connect to a suitable voltage

supply. The PG pin goes high with a typical 1.3ms delay time after VOUT is between 93% (typical) and 107%

(typical) of the target output voltage. When the output voltage is out of the target output voltage window, the PG

pin immediately goes low with a 33μs deglitch filter delay. This deglitch filter also prevents any false pulldown of

the PGOOD due to transients. When EN is pulled low, the PG pin is also forced low with a 33μs deglitch filter

delay. If not used, the PG pin can be left floating or connected to GND.

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TPSM81033

SLVSHL0B – JUNE 2024 – REVISED JULY 2024

Copyright © 2024 Texas Instruments Incorporated

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