MCP60713 datasheet(21/41 Pages) MICROCHIP

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DS20006870A-page 21

MCP60711/1U/3

4.2.2

PCB SURFACE LEAKAGE

In applications where maintaining low input currents is

critical, Printed Circuit Board (PCB) leakage currents

must be minimized. These PCB leakage currents are

mainly caused by humidity, dust or other contaminants

on the PCB surfaces.

The following techniques can help to reduce PCB

leakage currents:

• Place critical input traces in inner layers

• Use conformal coating

• Use guard rings where possible (packages with

tightly spaced pins can limit this approach)

4.2.3

LOW OFFSETS

4.2.3.1

Input Offset Voltage Errors

The data sheet parameters that describe DC voltage

errors at the op amp’s input, act as an increase of the

voltage at the noninverting input (see Figure 4-4).

These parameters are: VOS, TC1, TC2, CMRR, PSRR

and AOL (see the DC Electrical Specifications table).

FIGURE 4-4:

Op Amp Feedback Network.

The combined errors are:

EQUATION 4-6:

The error referred to VOUT is:

EQUATION 4-7:

Mechanical stresses on an op amp will change the

input offset voltage. Standard techniques to minimize

stresses on the PCB will minimize this issue.

4.2.3.2

Input Bias Current Errors

The Input Bias Current (IB) and Input Offset Current

(IOS) cause voltage drops across resistors in the circuit,

increasing the voltage errors. These currents are

positive when they go into the op amp, so the circuit in

Figure 4-4 gives:

EQUATION 4-8:

Note that the PCB leakage currents discussed in

Section 4.2.2, PCB Surface Leakage add additional

DC errors to the circuit. These errors depend on where

these currents are injected into the circuit. Standard

circuit analysis techniques will give the output error.

4.2.4

CAPACITIVE LOADS

Driving large capacitive loads can cause stability

problems for op amps. As the load capacitance

increases,

the

feedback

loop’s

phase

margin

decreases and the closed-loop bandwidth is reduced.

This produces gain peaking in the signal’s frequency

response (see Figure 2-43 and Figure 2-44) and

overshoot and ringing in the step response. A unity-

gain buffer (G = +1) is the most sensitive to capacitive

loads, though all gains show the same general

behavior. See Section 2.6, Capacitive Loads for plots

of typical behavior.

When driving large capacitive loads (e.g., CL >30pF

when G = +1), a small series resistor at the output

(RISO in Figure 4-5) improves the feedback loop’s

phase margin (stability) by making the output load

resistive at higher frequencies. The bandwidth will be

generally lower than the bandwidth with no capacitive

load.

FIGURE 4-5:

Compensating a Capacitive

Load (CL) with RISO.

Figure 2-45 gives recommended RISO values for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (CL/GN), where GN is the

MCP6071X

VIP

VOUT

VIM

VOST =VOS +TC1(TA – 25°C) + TC2(TA –25°C)2

+ ΔVCM/CMRR + ΔVOUT/AOL

+ Δ(VDD –VSS)/PSRR

Where:

VOST = total input offset voltage (error)

1/CMRR, 1/AOL and 1/PSRR have units of

µV/V (e.g., ±100 µV/V corresponds to 80 dB)

VOERR =GN VOST

Where:

VOERR = total output offset voltage (error)

GN = the

circuit’s

“Noise

Gain”

=1 + RF/RG,in Figure 4-4

VTIBE =(IB –IOS/2) (RF||RG)–(IB +IOS/2) RN

VTOBE =GN VTIBE

Where:

VTIBE = total input bias current error

VTOBE = total output bias current error

GN is defined in Equation 4-7

MCP6071X

VIN

VOUT

RISO

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