MCP60711/1U/3

DS20006870A-page 4

 2024 Microchip Technology Inc. and its subsidiaries

TABLE 1-2:

AC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = 25°C, VDD = 3.5V, VSS = GND, VCM = 0.1V, VOUT =VDD/2,

VL =VDD/2, RL =5kΩ to VL and CL = 30 pF; see Figure 1-7.

Parameters

Sym.

Min. Typ. Max. Units

Conditions

AC Response

Gain-Bandwidth Product

GBWP

—

10

—

MHz

VOUT =0.1 VP-P, GN >+2

Full Power Bandwidth

FPBW

—

1.1

—

VDD =5V, VCM = 2.5V, VOUT =4.6 VP-P, Gain = -1 V/V

Phase Margin

PM

—

65

—

°

G = +1, VOUT =0.1 VP-P

—45

—

G = +1, VOUT =0.1 VP-P, CL = 100 pF

Step Response

Settling Time

tsettle

—

110

—

ns

G = +1, VCM = 0.5V, +0.1V step and 1% settling

—

110

—

G = +1, VCM =VDD – 0.5V, +0.1V step and 1% settling

Slew Rate

SR

—

4.1

—

V/µs

G = +1, VDD =2.2V

—15

—

G = +1, VDD =5.5V

Output Overdrive

Recovery Time (Note 1)

tODR

—

0.9

—

µs

G = -10, VDD =3.5V, VCM =VDD/2, ±0.5V output overdrive

(VIN = VCM ± 0.225V to VCM), 90% of VOUT change

Noise

Input Noise Voltage

Eni

—3.1

—

µVP-P f = 0.1 Hz to 10 Hz, VCM =0.1V

—

5.9

—

f = 0.1 Hz to 10 Hz, VCM =VDD –0.5V

Input Noise Voltage

Density

eni

—5.4

—

nV/√Hz f = 100 kHz, VCM =0.1V

—

6.1

—

f = 100 kHz, VCM =VDD –0.5V

Input Current Noise

Density

ini

—0.6

—

fA/√Hz f = 1 kHz, VCM =0.1V

—

0.6

—

f = 1 kHz, VCM =VDD –0.5V

Harmonic Distortion – Output Nonlinearity

Total Harmonic Distortion

+Noise

THD+N

—

-115

—

dBc

GN = 1 V/V, f = 1 kHz, VOUT =2VP-P, VDD =5V, VCM =2V

EMI Protection

EMI Rejection Ratio

EMIRR

—

29

—

dB

VIN =0.1 VPK, f = 400 MHz

—50

—

VIN =0.1 VPK, f = 900 MHz

—71

—

VIN =0.1 VPK, f = 1800 MHz

—81

—

VIN =0.1 VPK, f = 2400 MHz

—112

—

VIN =0.1 VPK, f = 6000 MHz

Shutdown

Shutdown VOUT Turn On

Time

tSD_ON

—3.1

—

µs

IO = 0, VL = 0V, SHDN = 3.5V to 0V step, 90% of VOUT

change (Note 2)

Shutdown VOUT Turn Off

Time

tSD_OFF

—0.5

—

µs

IO = 0, VL = 0V, SHDN = 0V to 3.5V step, 90% of VOUT

change (Note 2)

Shutdown Setup Time

tSD_SU

—

0.5

—

µs

Minimum setup time between SHDN events (Note 2)

Note 1: tODR includes some uncertainty due to clock edge timing.

2: The POR must be on for the time tPON_TR before SHDN function is enabled; it is disabled when the POR is off.