Philips Semiconductors

Product specification

SC26C198 SC68C198

SC26L198 SC68L198

Octal UART with TTL compatibility at 3.3V

and 5V supply voltages

1995 May 1

375

SYMBOL

FIGURE

PARAMETER

LIMITS

UNIT

SYMBOL

FIGURE

PARAMETER

MIN

TYP

MAX

UNIT

Fx1

X1 clock frequency

0

3.6864

8.0

MHz

X1 L / H

X1 Low / High time

20

ns

T/RFx1

X1 Rise / Fall time

10/10

ns

COUNTER / TIMER BAUD RATE CLOCK (EXTERNAL CLOCK INPUT)

FC/T

Clock frequency

0

8

MHz

TC/TLH

C/T high and low time

30

ns

TC/TO

Delay C/T clock external to output pin

60

ns

DAKdly

DACK low from Sclk C4 rising edge

25

ns

DAKdlya

DACK high from CEN high (ASYNC)

28

40

ns

DAKdlys

DACK high from C4 end rising edge (SYNC)

28

40

ns

I/O PORT External Clock

Tgpirtx

GPI to Rx/Tx clock out

TBD

ns

RxD setup to I/OP rising edge 1X mode

TBD

ns

I/OP falling edge to TxD out 1X mode

TBD

ns

Gout TIMING

GPOtdd

GPO valid after write to GPOR

TBD

ns

NOTES:

1. The ASYNC pulse width low must include 4 rising edges plus the setup & hold times. For those applications where the control processor

has no knowledge of the Sclk period, this will imply a CEN period of 5 Sclk rising edges.

2. Production test will use rise and fall time less than 7ns. Specified rise and fall times are guaranteed by design.

3. Sclk is required for proper bus timing. Sclk must always be faster than twice the fastest 1X data clock.

4. The meaning of DACKN is that data will be valid before the end of the C4 time.

5. All voltage measurements are relative to gnd. Input and output levels are those shown in “DC Electrical Specifications”. For testing, inputs

switch between 0.2 and 2.8V; outputs are measured between 0.8 and 2.0V.